NXP Semiconductors QorIQ LS1012A Reference Manual

set to 1'b0 from the core since VBUS charging is notsupported in OTG 2.0 specifications.• The application should not program GCTL[0] as 1'b0 whenit wants to do a ADP or HNP. In such a case, theapplication should disable the Clock Gating feature byprogramming GCTL[0] as 1'b1. The application should re-enable the Clock Gating feature only when the core returnsto its original role of operation.33.4.6.1.1.1 HNP Polling and EnableThis HNP Polling activity involves an OTG device acting as the current host toperiodically poll the remote device to check if the remote device wishes to take the hostrole. It will then grant the role swap opportunity at the earliest opportunity. Being asoftware activity, HNP Polling is expected to be implemented through software timersand periodic exchange of SetFeature.SetHNPEnable packets.The core is then informed of successful exchange of these packets to Enable HNP activitywithin the core.33.4.6.1.2 ADP functionsThe ADP functions involve the following two processes:• ADP sensing• ADP probingADP probing capability is required in both A and B devices, while sensing is a must onlyfor B-Device. The main functional unit is the ADP controller.33.4.6.1.2.1 Internal ADP controller• All ADP timers are maintained in pwrm (Power) module and generate the enable anddisable signaling to PHY for ADP probing and sensing.• PHY contains the following circuitry related to ADP functionality:• Comparators for PRB and SNS• I_ADP_SRC and I_ADP_SNK• Vbus circuitry• Application software programs the ADP timing registers residing in the pwrmmodule.• pwrm module provides a mechanism to application through the interrupts to log andreport events pertaining to ADP probing and sensing.Functional DescriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20182302 NXP Semiconductors