NXP Semiconductors QorIQ LS1012A Reference Manual

Field Function0011b - SEQ_NAK0100b - Packet0101b - FORCE_ENABLE0110-1111b - Reserved, should be cleared16-17PICPICPort indicator control. Control the link indicator signals. These signals are valid for host mode only.This field is output from the controller for use by an external LED driving circuit.00b - Off01b - Amber10b - Green11b - Undefined18POPOPort owner. Unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is zero. System softwareuses this field to release ownership of the port to a selected module (in the event that the attached deviceis not a high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that an internal companion controller owns and controls the port.Port owner hand-off is not implemented in this design, therefore this bit is always 0.19PPPPPort power. Represents the current setting of the switch (0=off, 1=on). When power is not available on aport (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, and so on.When an over-current condition is detected on a powered port, the PP bit in each affected port istransitioned by the host controller driver from a one to a zero (removing power from the port).This feature is implemented in the host controller (PPC = 1).In a device-only implementation port power control is not necessary, thus PPC and PP = 0.0b - USBDR writes 0 for DRVVBUS bit of OTGControl register in PHY.1b - USBDR writes 1 for DRVVBUS bit of OTGControl register in PHY. The OTG Control register isdefined in ULPI specification.20-21LSLSLine status. Reflect the current logical levels of the USB D+ (bit 11) and D- (bit 10) signal lines. The useof line status by the host controller driver is not necessary (unlike EHCI), because the connection of FSand LS is managed by hardware.00b - SE001b - K-state10b - J-state11b - Undefined22—-Reserved, should be cleared23PRPRPort reset.Host mode:• When software writes a one to this bit the bus-reset sequence as defined in the USB SpecificationRevision 2.0 is started. This bit will automatically change to zero after the reset sequence iscomplete. This behavior is different from EHCI where the host controller driver is required to set thisbit to a zero after the reset duration is timed in the driver.Device mode:Table continues on the next page...USB register descriptionsQorIQ LS1012A Reference Manual, Rev. 1, 01/20181942 NXP Semiconductors