NXP Semiconductors QorIQ LS1012A Reference Manual

Like the system interface block, the DMA engine block uses a simple synchronous bussignaling protocol that eases connections to a number of different standard buses.The DMA controller must access both control information and packet data from systemmemory. The control information is contained in link list-based queue structures. TheDMA controller has state machines that are able to parse data structures defined in theEHCI specification. In host mode, the data structures are EHCI compliant and representqueues of transfers to be performed by the host controller, including the split-transactionrequests that allow an EHCI controller to direct packets to FS and LS devices. In devicemode, the data structures are designed to be similar to those in the EHCI specificationand are used to allow device responses to be queued for each of the active pipes in thedevice.32.4.3 FIFO RAM controllerThe FIFO RAM controller is used for context information and to control FIFOs betweenthe protocol engine and the DMA controller.These FIFOs decouple the system processor/memory bus requests from the extremelytight timing required by USB.The use of the FIFO buffers differs between host and device mode operation. In hostmode, a single data channel is maintained in each direction through the buffer memory.In device mode, multiple FIFO channels are maintained for each of the active Endpointsin the system.In host mode, the USB DR module uses a 512-byte Tx buffer and a 512-byte Rx buffer.Device operation uses a single 512-byte Rx buffer and a 512-byte Tx buffer for eachEndpoint. The 512-byte buffers allow the module to buffer a complete HS bulk packet.32.4.4 PHY interfaceThe ULPI interface connects to an external PHY. The USB DR module interfaces to anyULPI-compatible PHY.The primary function of the port controller block is to isolate the rest of the module fromthe transceiver, and to move all of the transceiver signaling into the primary clockdomain of the module.This allows the module to run synchronously with the system processor and its associatedresources.Functional descriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20181968 NXP Semiconductors