NXP Semiconductors QorIQ LS1012A Reference Manual

29.5.3 Central Security UnitThe Central Security Unit (CSU) allows secure world software to change the defaultaccess control policies of peripherals/bus slaves, determining which bus masters mayaccess them. This allows peripherals to be separated into distinct security domains.29.5.4 Platform ControlThe platform control stores the status and address attributes of the blocked/failedtransactions to the target IP modules whose access controls are defined by CSU registerbits and also raise an interrupt and security violation to security monitor.For more details, refer Miscellaneous System Control Module (MSCM).29.5.5 Arm generic interrupt controller (GIC)The Generic interrupt controller (GIC) is a centralized resource for supporting andmanaging interrupts from peripherals to at least one general purpose Arm processor.In the context of the Trust Architecture, the Arm GIC supports virtualized interrupts(interrupt delivered to a specific virtual machine) and to secure world. The GIC registerssupport configuration by TZ secure world, and prevents non-secure world software fromdisabling or clearing the interrupts of peripherals controlled by TZ secure world.29.5.6 TrustZone Watchdog (TrustZone WDOG)The TrustZone WDOG is an additional watchdog timer instance that cannot beprogrammed or deactivated from TZ non-secure world.. The TrustZone WDOG protectsagainst TZ non-secure world software preventing a switch back to the Secure World,thereby starving security services of access to GPP resources. Once the TrustZoneWDOG is activated, it must be serviced by TZ secure world software on a periodic basis.If servicing does not take place before the configured time-out, the TrustZone WDOGasserts a secure interrupt that forces a switch to the Secure World. If it is still not served,the TrustZone WDOG generates a hardware security violation to the Security Monitor(see Security monitor).The TrustZone WDOG requires a non-gateable clock source, and should be capable ofcounting up to 256 seconds.Trust Architecture as implemented on the chipQorIQ LS1012A Reference Manual, Rev. 1, 01/20181740 NXP Semiconductors