NXP Semiconductors QorIQ LS1012A Reference Manual

Table 33-20. Non-isochrnous IN transfers (continued)Step 6 Non-SS host issues atoken request. SS hostissues ACK TP torequest data.- -Step 7 - Since DMA is not set up, the device sends s NAK inNon- SS mode, or NRDY in SS mode, to the host. Thecore also generates an XferNotReady event-Step 8 - - On seeing theXferNotReady event,software sets up NormalTRBs and enables DMAby issuing Start Transfer.Step 9 - Steps 2-5 are followed. -Step 10 - When software knows it is talking to a host that alwaysends transfers with short packets, and therefore alwaysrequires a zero-byte packet to end a transfer, it includesa zero-byte TRB (CHN=0) after the last TRB which is aneven multiple of MaxPacketSize.When software does not know if the host is going to doanother IN token after receiving the exact number ofbytes it expected (and it was a multiple of MPS), it doesnot include a zero-byte TRB, and sets LST in the lastTRB. If the host returns with another IN for a zero-bytepacket, it uses the XferNotReady/Start Transfermechanism to add one zero-byte TRB. This is called"On- Demand."-33.4.3.2.5.4 Isochronous IN TransfersThis section describes the difference between isochronous and non-isochronous INtransfers referring to the sequence in Non-isochronous IN transfers.• In Step 4, if the TXFIFO is empty when host IN request arrives, the core returns azero length packet in both Non-SS and SS modes.• In Step 7, the device returns zero length packet and generates an XferNotReadyevent.Special scenarios:• When data is fetched and there is no request from the host (possibly due to a missingrequest or corrupted request) the data will be flushed at the end of the service interval(corresponding Micro- Frame) boundary and the core moves onto fetching nextservice interval data. If there are some TRBs that are not serviced in the serviceinterval, the core will skip these TRBs.• If the core encounters control bits LST or IOC, it will generate an event, and in thecase of LST TRB, the stream will be completed, but has to reclaim TRBs if anyTRBs skipped with HWO=1.Functional DescriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20182268 NXP Semiconductors