NXP Semiconductors QorIQ LS1012A Reference Manual

If siTDX-1's Active bit is cleared, (because it was cleared when the host controller firstvisited siTDX-1 via siTDX's back pointer, it transitioned to zero as a result of a detectederror, or the results of siTDX-1's complete-split transaction cleared it), then the hostcontroller returns to the context of siTDX and transitions its SplitXState to Do Start Split.The host controller then determines whether the case 2b start split boundary conditionexists (that is, if cMicroframeBit is 1 and siTDX[S-mask[0]] is 1). If this criterion is metthe host controller immediately executes a start-split transaction and appropriatelyadvances the transaction state of siTDX, then follows siTDX[Next Pointer] to the nextschedule item. If the criterion is not met, the host controller simply follows siTDX[NextPointer] to the next schedule item. Note that in the case of a 2b boundary case, the split-transaction of siTDX-1 will have its Active bit cleared when the host controller returns tothe context of siTDX. Also, note that software should not initialize an siTD with C-maskbits 0 and 1 set and an S-mask with bit 0 set. This scheduling combination is notsupported and the behavior of the host controller is undefined.32.6.12.3.7 Split transaction for isochronous-processing exampleThere is an important difference between how the hardware/software manages theisochronous split transaction state machine and how it manages the asynchronous andinterrupt split transaction state machines.The asynchronous and interrupt split transaction state machines are encapsulated within asingle queue head. The progress of the data stream depends on the progress of each splittransaction. In some respects, the split-transaction state machine is sequenced using theExecute Transaction queue head traversal state machine.Isochronous is a pure time-oriented transaction/data stream. The interface data structuresare optimized to efficiently describe transactions that need to occur at specific times. Theisochronous split-transaction state machine must be managed across these time-orienteddata structures. This means that system software must correctly describe the schedulingof split-transactions across more than one data structure.Then the host controller must make the appropriate state transitions at the appropriatetimes, in the correct data structures.For example, the table below illustrates a few frames worth of scheduling required toschedule a case 2a full-speed isochronous data stream.Table 32-43. Example case 2a-software scheduling siTDs for an IN endpointsiTDX Micro-frames InitialSplitXState# Masks 0 1 2 3 4 5 6 7X S-mask 1 Do start splitC-mask 1 1 1 1Table continues on the next page...Chapter 32 Universal Serial Bus Interface 2.0QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 2055