NXP Semiconductors QorIQ LS1012A Reference Manual

29.8.3.1 Instruction Register (SFP_INGR)The instruction register (INGR) is the target of software commands intended to read orprogram the SFP fuse array. As the values in the instruction register are not reflected inthe fuse array, there is no write protection for this register. When programming the SFPfuse array, polling INST and ERR provides confirmation that the SFP logic hascompleted burning fuses. If INST = 00 and ERR = 0, the PROGFB event has completedsuccessfully.Address: 1E8_0000h base + 20h offset = 1E8_0020hBit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R ReservedWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R Reserved ERR INSTWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SFP_INGR field descriptionsField Description0–22-This field is reserved.Reserved23ERRError status. ERR clears on a write to INST, and becomes valid when INST clears.0 Transaction completed successfully.1 An error occurred during the transaction.24–31INSTInstruction. INST will clear to IDLE upon completion of any instruction.00 IDLE. SFP is not actively processing an instruction.01 READFB. Read the entire fusebox and load the contents into the corresponding mirror registers.10 PROGFB. Permanently write data from the mirror registers into the fuse array.29.8.3.2 Secret Value Hamming Error Status Register (SFP_SVHESR)NOTETo better understand the functionality of this register, the readeris advised to first review Debug Response Value Register n(SFP_DRVRn) and One Time Programmable Master Key n(SFP_OTPMKRn).Security fuse processor (SFP)QorIQ LS1012A Reference Manual, Rev. 1, 01/20181758 NXP Semiconductors