NXP Semiconductors QorIQ LS1012A Reference Manual

23.3.4.1 Power saving generalMMDC supports multiple DDR power saving modes.NOTEBy default, the power saving modes are disabled. These modesmay dramatically decrease the power consumption of DDRmemories.1. Self-refresh entry to the entire DDR device can be activated through twomechanisms:• LPMD (Low Power Mode)• Hardware handshaking (LPMD/LPACK) with the clock module in thesystem• Software handshaking by setting the field MAPSR[LPMD] and pollingMAPSR[LPACK]• Automatic entry by configuring the amount of idle cycle for triggering self-refresh entry through MAPSR[PST] and by clearing MAPSR[PSD]• DVFS (Dynamic Voltage and Frequency Change)• Software handshaking by setting the field MAPSR[DVFS] and pollingMAPSR[DVACK]NOTEIf hardware or software requests for self-refresh entry weredetected by the MMDC (even before the assertion of theLPACK), no write or read accesses will be acknowledgedutnil the deassertion of those requests.2. Automatic active/precharge power down entry to a specific chip select can beactivated by configuring the MDPDC register:• PWDT_0 - defines the number of idle cycles before entering power down.• SLOW_PD - In case of slow precharge power down then this bit should be set aswell.• Few paramters must be configured in addition:• Timing parameters at MDCFG0[tXP and tXPDLL].• ODT timing at MDOTC[tAOFPD, tAONPD, tANPD and tAXPD]NOTEIt is possible to enter certain chip selects to low powerconsumption while the second chip select is activated.3. Automatic precharge of all DDR banks to a specific chip select. Can be activated byconfiguring MDPDC field: PRCT_0.Functional DescriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20181086 NXP Semiconductors