NXP Semiconductors QorIQ LS1012A Reference Manual

Field FunctionDWC_USB3_RM_OPT_FEATURESWhen this parameter is enabled, the user ID register, General Purpose Input/Output ports, and SOFtoggle and counter ports are removed.0b - No1b - Yes29—Reserved28DWC_USB3_RAM_BUS_CLKS_SYNCIt specifies whether the RAM clock and the Bus clock are synchronous to each other.0b - No1b - Yes27DWC_USB3_MAC_RAM_CLKS_SYNCIt specifies whether the MAC clock and the RAM clock are synchronous to each other.0b - No1b - Yes26DWC_USB3_MAC_PHY_CLKS_SYNCIt specifies whether the MAC clock and the PHY clock are synchronous to each other.0b - No1b - Yes25-24DWC_USB3_EN_PWROPTPower optimization modeIt specifies the power optimization mode.If clock gating only is selected, RAM and PHY clocks are gated when the core is inactive during U1, U2,or U3 states.00b - No power optimization01b - Clock gating only10b - Reserved11b - Reserved23DWC_USB3_SPRAM_TYPSynchronous static RAM typeIt selects the FIFO synchronous static RAM type.0b - 2-port RAM (2Port-RAM)1b - Single-port RAM (SPRAM)22-21DWC_USB3_NUM_RAMSNumber of RAMsIt selects the number of RAMs.The possible values are 1, 2 and 3.20-15DWC_USB3_DEVICE_NUM_INTNumber of device mode event buffersIt selects the number of event buffers in device mode.The possible values are 1, 2,..., and 32.14-12DWC_USB3_ASPACEWIDTHIt selects the address space port width of the master and slave bus interfaces.The possible values are 1, 2, 3, 4, 5 and 6.11-9DWC_USB3_REQINFOWIDTHIt selects the request/response info port width of the master and slave bus interfaces.The possible values are 4, 5 and 6.8-6 It selects the data info port width of the master and slave bus interfaces.The possible values are 1, 2, 3, 4, 5 and 6.Table continues on the next page...USB3.0 register descriptionsQorIQ LS1012A Reference Manual, Rev. 1, 01/20182150 NXP Semiconductors