NXP Semiconductors QorIQ LS1012A Reference Manual

27.3.16.3 DiagramBits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R PMPRA POE PRTWReset 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RAIREPNRTS4ARXSETXSETXPJTXCRXBCTXBCWReset 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 027.3.16.4 FieldsField Function31-27PMPRAPower management primitive rate acknowledgeThis bit determines the number of PMACK primitives sent when a power management state transition isrequested by the host.26POEPrimitive override enableWhen set, this bit enables the replacement of a single primitive, as specified by override primitive/CD,when the link layer state machine is in the Prim override state. This bit must be set to enable this feature.25-16PRTPHY Ready timerThis bit specifies the timeout value of the PHY Ready timer. If EnPhyReadyTimeOut is set, the link layercounts down on every rising edge of TX clock, as long as PHY Ready is de-asserted. When the counterreaches zero, a PhyReset is issued to the PHY to try and re-establish communications with the far-end.The timer is initially loaded with a value equal to the concatenation of { PHY Ready Timer, 9’h000}.15-8AIRALIGN insertion rateThe SATA AHCI Specification requires that the link layer sends a pair of ALIGN primitives at least every254 DWords of data. This is achieved by setting ALIGN insertion rate to "11111111". However, for testpurposes it is possible to send ALIGNs at a higher rate. This can be achieved by setting ALIGN insertionrate to a lower value i.e. (ALIGN insertion rate-1). DWords are sent by the link layer between each set ofALIGN primitive pairs.NOTE: If the S4A bit is set, the ALIGN insertion rate should not be set to four or less. If S4A is not set,the ALIGN insertion rate should not be set to two or less.7EPNRTEnable PHY not ready timerIf PHY Ready is de-asserted for a long time as specified by PRT bit, then this bit, when asserted, enablesthe link layer to re-issue a PhyReset, thereby re-initiating OOB.6S4ASend 4 AlignsIf this bit is asserted, four ALIGN primitives are transmitted at the specified rate, instead of the normal twoALIGN primitives.5RXSERx scramble enableTable continues on the next page...SATA AHCI register descriptionsQorIQ LS1012A Reference Manual, Rev. 1, 01/20181542 NXP Semiconductors