Table 26-20. Instruction setInstruction Instructionencoding Pins Operand Action on Serial Flash(es)CMD 6'd1 N=2'd{0,1,2}2'd0 - Onepad2'd1 - Twopads2'd2 - Fourpads8 bitcommandvalueProvide the serial flash with operand on the number of padsspecifiedADDR 6'd2 Number ofaddress bitsto be sent (forexample,8'd24 => 24address bitsrequired)Provide the serial flash with address cycles according to theoperand on the number of pads specified. The actual addressto be provided will be derived from the incoming address incase of AHB initiated transactions and the value of SFAR incase of IPS initiated transactions .DUMMY 6'd3 Number ofdummy clockcycles (shouldbe <= 64cycles)Provide the serial flash with dummy cycles as per theoperand. The PAD information defines the number of pads ininput mode. (for example, one pad implies that pad 1 is notdriven, rest all are driven)MODE 6'd4 8 bit modevalueProvide the serial flash with 8 bit operand on the number ofpads specifiedMODE2 6'd5 N=2'd{0,1} 2 bit modevalueProvide the serial flash with 2 bit operand on the number ofpads1 specifiedMODE4 6'd6 N=2'd{0,1,2} 4 bit modevalueProvide the serial flash with 4 bit operand on the number ofpads2 specifiedREAD 6'd7 N=2'd{0,1,2}2'd0 - Onepad2'd1 - Twopads2'd2 - FourpadsRead datasize in bytes(for AHBtransactions,the user'sapplicationshould ensurethat data sizeis a multiple of8 bytes)Read data from flash on the number of pads specified. Thedata size may be overwritten by writing to the ADATSZ field ofthe QSPI_BUFxCR registers for AHB initiated transactionsand IDATSZ field of IP Configuration Register(QuadSPI_IPCR) for IP initiated transactions.WRITE 6'd8 Write datasize in bytesWrite data on number of pads sepcified. The data size maybe overwritten by writing to the IDATSZ field of IPConfiguration Register (QuadSPI_IPCR) registerJMP_ON_CS 6'd9 NA InstructionnumberEvery time the chip select (CS) is deasserted, jump to theinstruction pointed to by the operand. This instruction allowsthe programmer to specify the behavior of the controller whena new read transaction is initiated following a CS deassertion.STOP 8'd0 NA NA Stop execution; deassert CS1. For a one pad instruction, MODE2 will take 2 serial flash clock cycles on the flash interface.2. For a one pad instruction, MODE4 will take 4 serial flash clock cycles on the flash interface. For a 4 pad instruction,MODE4 will take 1 serial flash clock cycle on the flash interface.The programmable sequence engine allows the user to configure the QuadSPI moduleaccording to the serial flash connected on board. The flexible structure is easily adaptableto new command/protocol changes from different vendors.Functional DescriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20181480 NXP Semiconductors