NXP Semiconductors QorIQ LS1012A Reference Manual

33.4.3.3.9.1 FIFO-based isochronous IN EndpointsThe software of some applications is unable to keep up with the short latency and highbandwidth of isochronous traffic and require the data to be sourced and done a syncthrough external FIFOs. One example is that there are two external TXFIFOs, one foreach interval, and an address-to-FIFO-pop logic is implemented so that when the coreattempts to read from interval 1's address, the translation logic converts this into a popsignal for interval 1's TXFIFO. When the core attempts to read from interval 2's address,the translation logic converts this into a pop signal for interval 2's TXFIFO.To describe a FIFO-based implementation, software sets up an endpoint with the "FIFO-based" configuration bit set. This type of endpoint ignores the HWO bit in all TRBs,assuming that the TRB is always valid, and that the core should never write it back.Software chooses the buffer pointers within the TRBs to correspond to the addressneeded by the translation logic to specify which FIFO should be popped. By also usingthe CHN bit, headers and payload can be concatenated from different FIFOs. Forexample, if there are 4 external FIFOs: HA, PA, HB, PB, where HA/HB contain the 4byte header for 2 intervals and PA/PB contain the 512 byte payload for 2 intervals, thiscan be described by using the following 5 TRBs:1. BUFPTR=HA, IOC=0, CHN=1, BUFSIZ=42. BUFPTR=PA, IOC=1, CHN=0, BUFSIZ=5123. BUFPTR=HB, IOC=0, CHN=1, BUFSIZ=44. BUFPTR=PB, IOC=1, CHN=0, BUFSIZ=5125. Link to (1)Every interval, the core will be creating a 516 byte packet that consists of 4 bytes fromthe header FIFO and 512 bytes from the payload FIFO. However, if the host does not pollfor the packet, the core will skip 1 or 2 intervals of popping, depending on whether it hasalready started reading the next interval. External logic (or software) is responsible forflushing and refilling alternate FIFOs so that the core is always reading the correct datafor the next interval. In normal intervals, the FIFOs will be empty, but when an interval ismissed, there may still be data present in the FIFOs.Software Requirements:• The "FIFO-based" bit must be set in the DEPCFG when configuring the endpoint.• No field within any TRB may be changed after the Start Transfer command is issued.• Data must be valid in the external FIFO at least 1 uF before the beginning of theinterval for which the data is intended.Core Behavior:• The earliest the core will read from the FIFO will be 1 μF before the beginning of theinterval for which the data is intended.Functional DescriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20182278 NXP Semiconductors