NXP Semiconductors QorIQ LS1012A Reference Manual

30.5.6.1 Parity for SPI FramesWhen the module is in the master mode the parity generation is controlled by PE and PPbits of the CMD FIFO entries (PUSHR). Setting the PE bit enables parity generation fortransmitted SPI frames and parity check for received frames. PP bit defines polarity ofthe parity bit.When continuous PCS selection is used to transmit SPI data, two parity generationscenarios are available:• Generate/check parity for the whole frame• Generate/check parity for each sub-frame separately.To generate/check parity for the whole frame set PE bit only in the last command/TXFIFO entry, forming this frame (with the PUSHR register).To generate/check parity for each sub-frame set PE bit in each command/TX FIFO entry,forming this frame.If the parity error occurs for received SPI frame, the SR[SPEF] bit is set. If MCR[PES]bit is set, the module stops SPI frames transmission. To resume SPI operation clear theSR[SPEF] or the MCR[PES] bits.30.5.7 Interrupts/DMA requestsThe module has several conditions that can generate only interrupt requests and twoconditions that can generate interrupt or DMA requests. The following table lists theseconditions.Table 30-15. Interrupt and DMA request conditionsCondition Flag Interrupt DMAEnd of Queue (EOQ) EOQF Yes -TX FIFO Fill TFFF Yes YesCMD FIFO Fill CMDFFF Yes YesTX FIFO Invalid Write TFIWF Yes -Transfer Complete TCF Yes -CMD Transfer Complete CMDTCF Yes -TX FIFO Underflow TFUF Yes -RX FIFO Drain RFDF Yes YesRX FIFO Overflow RFOF Yes -SPI Parity Error SPEF Yes -Functional descriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20181852 NXP Semiconductors