6.2.2.1.1 Reset pin filterThe RESET pin filter supports filtering from both the 1 kHz LPO clock and the busclock. The RPFC[RSTFLTSS], RPFC[RSTFLTSRW], and RPFW[RSTFLTSEL] fieldsin the reset control (RCM) register set control this functionality; see the RCM chapter.The filters are asynchronously reset by Chip POR. The reset value for each filter assumesthe RESET pin is negated.For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, andVLLS1), the only filtering option is the LPO based digital filter. The filtering logic eitherswitches to bypass operation or has continued filtering operation depending on thefiltering mode selected. When entering VLLS0, the RESET pin filter is disabled andbypassed.The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, thereis also some associated latency (2 cycles). As a result, 5 cycles are required to complete atransition from low to high or high to low.6.2.2.2 Low-voltage detect (LVD)The chip includes a system for managing low voltage conditions to protect memorycontents and control MCU system states during supply voltage variations. The systemconsists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable tripvoltage. The LVD system is always enabled in normal run, wait, or stop mode. The LVDsystem is disabled when entering VLPx, LLS, or VLLSx modes.The LVD can be configured to generate a reset upon detection of a low voltage conditionby setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold isdetermined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, theLVD system holds the MCU in reset until the supply voltage has risen above the lowvoltage detection threshold. The RCM's SRS0[LVD] bit is set following either an LVDreset or POR.6.2.2.3 Computer operating properly (COP) watchdog timerThe computer operating properly (COP) watchdog timer (WDOG) monitors the operationof the system by expecting periodic communication from the software. Thiscommunication is generally known as servicing (or refreshing) the COP watchdog. If thisperiodic refreshing does not occur, the watchdog issues a system reset. The COP resetcauses the RCM's SRS0[WDOG] bit to set.Chapter 6 Reset and BootKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 113
