Address: F000_0000h base + 4h offset = F000_0004hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16REN0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0HALTREQRAMPRIVSFRWPRIVTSTOPENTSTARTENMASKWReset 0 0 0 0 0 0 0 0 1 0 0 x* x* x* x* x** Notes:x = Undefined at reset.•MTB_MASTER field descriptionsField Description31ENMain trace enable bitWhen this bit is 1, trace data is written into the RAM memory location addressed byMTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto increments after the trace datapacket is written.The EN bit can be automatically set to 0 using the MTB_FLOW[WATERMARK] field and theMTB_FLOW[AUTOSTOP] bit.The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH.The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH.NOTE: If the EN bit is set to 0 because the MTB_FLOW[WATERMARK] field is set, then it is notautomatically set to 1 if the TSTARTEN bit is 1 and the TSTART input is HIGH. In this case,tracing can only be restarted if the MTB_FLOW[WATERMARK] or MTB_POSITION[POINTER]value is changed by software.30–10ReservedThis field is reserved.This read-only field is reserved and always has the value 0.9HALTREQHalt request bitThis bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1,the EDBFGRQ is asserted if DBGEN (invasive debug enable, one of the debug authentication interfacesignals) is also HIGH. The HALTREQ bit can be automatically set to 1 using theMTB_FLOW[WATERMARK] field.8RAMPRIVRAM privilege bitIf this bit is 0, then user or privileged AHB read and write accesses to the RAM are permitted. If this bit is1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses areRAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference.7SFRWPRIVSpecial Function Register Write Privilege bitIf this bit is 0, then user or privileged AHB read and write accesses to the MTB_RAM Special FunctionRegisters (programming model) are permitted. If this bit is 1, then only privileged write accesses areTable continues on the next page...Memory Map and Register DefinitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012276 Freescale Semiconductor, Inc.
