NOTEAny wait states inserted by the peripheral slave device(sx_hready = 0) are simply passed through the BME back to themaster input bus, stalling the AHB transaction cycle for cycle.17.4.1.1 Decorated Store Logical AND (AND)This command performs an atomic read-modify-write of the referenced memory location.First, the location is read; it is then modified by performing a logical AND operationusing the write data operand sourced for the system bus cycle; finally, the result of theAND operation is written back into the referenced memory location.The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)or word (32-bit). The core performs the required write data lane replication on byte andhalfword transfers.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0ioandb 0 1 0 0 0 1 - - - - - - mem_addrioandh 0 1 0 0 0 1 - - - - - - mem_addr 0ioandw 0 1 0 0 0 1 - - - - - - mem_addr 0 0Figure 17-3. Decorated store address: logical ANDwhere addr[28:26] = 001 specifies the AND operation, and mem_addr[19:0] specifies theaddress offset into the peripheral space based at 0x4000_0000. The "-" indicates anaddress bit "don't care".The decorated AND write operation is defined in the following pseudo-code as:ioand(accessAddress, wdata) // decorated store ANDtmp = mem[accessAddress & 0xE00FFFFF, size] // memory readtmp = tmp & wdata // modifymem[accessAddress & 0xE00FFFFF, size] = tmp // memory writewhere the operand size is defined as b(yte, 8-bit), h(alfword, 16-bit) and w(ord, 32-bit). This notation is used throughout the document.In the cycle definition tables, the notation AHB_ap and AHB_dp refers to the address anddata phases of the BME AHB transaction. The cycle-by-cycle BME operations aredetailed in the following table.Functional DescriptionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012244 Freescale Semiconductor, Inc.
