Table 3-27. KL04 flash memory sizeDevice Program flash (KB) Block 0 (P-Flash) address rangeMKL04Z8VFK4 8 0x0000_0000 – 0x0000_1FFFMKL04Z16VFK4 16 0x0000_0000 – 0x0000_3FFFMKL04Z32VFK4 32 0x0000_0000 – 0x0000_7FFFMKL04Z8VLC4 8 0x0000_0000 – 0x0000_1FFFMKL04Z16VLC4 16 0x0000_0000 – 0x0000_3FFFMKL04Z32VLC4 32 0x0000_0000 – 0x0000_7FFFMKL04Z8VFM4 8 0x0000_0000 – 0x0000_1FFFMKL04Z16VFM4 16 0x0000_0000 – 0x0000_3FFFMKL04Z32VFM4 32 0x0000_0000 – 0x0000_7FFFMKL04Z16VLF4 16 0x0000_0000 – 0x0000_3FFFMKL04Z32VLF4 32 0x0000_0000 – 0x0000_7FFF3.6.1.2 Flash Memory MapThe flash memory and the flash registers are located at different base addresses as shownin the following figure. The base address for each is specified in System memory map.Program flashFlash configuration fieldProgram flash base addressFlash memory base addressRegistersFigure 3-17. Flash memory mapThe on-chip Flash is implemented in a portion of the allocated Flash range to form acontiguous block in the memory map beginning at address 0x0000_0000. See FlashMemory Sizes for details of supported ranges.Accesses to the flash memory ranges outside the amount of Flash on the device causesthe bus cycle to be terminated with an error followed by the appropriate response in therequesting bus master. Read collision events in which flash memory is accessed while aflash memory resource is being manipulated by a flash command also generates a buserror response.Chapter 3 Chip ConfigurationKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 67
