6.2.2.4 Low leakage wakeup (LLWU)The LLWU module provides the means for a number of external pins and a number ofinternal peripherals to wake the MCU from low leakage power modes. The LLWUmodule is functional only in low leakage power modes. In VLLSx modes, all enabledinputs to the LLWU can generate a system reset.After a system reset, the LLWU retains the flags indicating the input source of the lastwakeup until the user clears them.NOTESome flags are cleared in the LLWU and some flags arerequired to be cleared in the peripheral module. Refer to theindividual peripheral chapters for more information.6.2.2.5 Multipurpose clock generator loss-of-clock (LOC)The MCG module supports an external reference clock.If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If theexternal reference falls below floc_low or floc_high, as controlled by the C2[RANGE] fieldin the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate thisreset source.NOTETo prevent unexpected loss of clock reset events, all clockmonitors must be disabled before entering any low powermodes, including VLPR and VLPW.6.2.2.6 Stop mode acknowledge error (SACKERR)This reset is generated if the core attempts to enter stop mode or Compute Operation, butnot all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock.A module might not acknowledge the entry to stop mode if an error condition occurs. Theerror can be caused by a failure of an external clock input to a module.ResetKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012114 Freescale Semiconductor, Inc.
