NXP Semiconductors MKL04Z8VFK4 Reference Manual Manual pdf 257 page image
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NXP Semiconductors MKL04Z8VFK4 Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Overview
  27. Typographic notation
  28. KL04 Sub-Family Introduction
  29. Module functional categories
  30. System Modules
  31. Memories and Memory Interfaces
  32. Analog modules
  33. Communication interfaces
  34. Introduction
  35. KL04 Sub-Family Reference Manual, Rev. 3.1, November
  36. Analog reference options
  37. Core Modules
  38. Nested Vectored Interrupt Controller (NVIC) Configuration
  39. Asynchronous wake-up interrupt controller (AWIC) configuration
  40. System Mode Controller (SMC) Configuration
  41. Low-Leakage Wake-up Unit (LLWU) Configuration
  42. MCM Configuration
  43. Crossbar-Light Switch Configuration
  44. Peripheral Bridge Configuration
  45. DMA request multiplexer configuration
  46. DMA Controller Configuration
  47. Clock Modules
  48. OSC Configuration
  49. Flash Memory Controller Configuration
  50. Analog
  51. CMP Configuration
  52. Timers
  53. PIT Configuration
  54. Low-power timer configuration
  55. RTC configuration
  56. I2C Configuration
  57. Human-machine interfaces (HMI)
  58. Memory Map
  59. Flash Memory Map
  60. Alternate Non-Volatile IRC User Trim Description
  61. Peripheral bridge (AIPS-Lite) memory map
  62. Modules Restricted Access in User Mode
  63. Clock definitions
  64. Device clock summary
  65. Internal clocking requirements
  66. VLPR mode clocking
  67. PMC 1-kHz LPO clock
  68. LPTMR clocking
  69. UART clocking
  70. Power-on reset (POR)
  71. MCU Resets
  72. Reset Pin
  73. Debug resets
  74. Boot
  75. DMA Wakeup
  76. Compute Operation
  77. Peripheral Doze
  78. Clock Gating
  79. Entering and exiting power modes
  80. Security Interactions with Debug
  81. SWD status and control registers
  82. MDM-AP Control Register
  83. MDM-AP Status Register
  84. Micro Trace Buffer (MTB)
  85. Port control and interrupt module features
  86. KL04 Pinouts
  87. Module Signal Description Tables
  88. Modes of operation
  89. Detailed signal description
  90. Pin Control Register n (PORTx_PCRn)
  91. Global Pin Control Low Register (PORTx_GPCLR)
  92. Global Pin Control High Register (PORTx_GPCHR)
  93. Functional description
  94. Global pin control
  95. System Options Register 1 (SIM_SOPT1)
  96. System Options Register 2 (SIM_SOPT2)
  97. System Options Register 4 (SIM_SOPT4)
  98. System Options Register 5 (SIM_SOPT5)
  99. System Options Register 7 (SIM_SOPT7)
  100. System Device Identification Register (SIM_SDID)
  101. System Clock Gating Control Register 4 (SIM_SCGC4)
  102. System Clock Gating Control Register 5 (SIM_SCGC5)
  103. System Clock Gating Control Register 6 (SIM_SCGC6)
  104. System Clock Gating Control Register 7 (SIM_SCGC7)
  105. System Clock Divider Register 1 (SIM_CLKDIV1)
  106. Flash Configuration Register 1 (SIM_FCFG1)
  107. Flash Configuration Register 2 (SIM_FCFG2)
  108. Unique Identification Register Mid-High (SIM_UIDMH)
  109. Service COP Register (SIM_SRVCOP)
  110. Memory map and register descriptions
  111. Power Mode Control register (SMC_PMCTRL)
  112. Stop Control Register (SMC_STOPCTRL)
  113. Power Mode Status register (SMC_PMSTAT)
  114. Power mode entry/exit sequencing
  115. Run modes
  116. Wait modes
  117. Stop modes
  118. Debug in low power modes
  119. LVD reset operation
  120. Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)
  121. Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)
  122. Regulator Status And Control register (PMC_REGSC)
  123. Block diagram
  124. LLWU signal descriptions
  125. LLWU Pin Enable 1 register (LLWU_PE1)
  126. LLWU Pin Enable 2 register (LLWU_PE2)
  127. LLWU Module Enable register (LLWU_ME)
  128. LLWU Flag 1 register (LLWU_F1)
  129. LLWU Flag 3 register (LLWU_F3)
  130. LLWU Pin Filter 1 register (LLWU_FILT1)
  131. LLWU Pin Filter 2 register (LLWU_FILT2)
  132. LLS mode
  133. System Reset Status Register 1 (RCM_SRS1)
  134. Reset Pin Filter Control register (RCM_RPFC)
  135. Reset Pin Filter Width register (RCM_RPFW)
  136. Memory Map and Register Definition
  137. Additional Details on Decorated Addresses and GPIO Accesses
  138. Application Information
  139. Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  140. Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
  141. Compute Operation Control Register (MCM_CPO)
  142. Features
  143. MTB_DWT Memory Map
  144. Arbitration
  145. Initialization/application information
  146. General operation
  147. External signal description
  148. DMA channels with periodic triggering capability
  149. Freescale Semiconductor, Inc
  150. DMA channels with no triggering capability
  151. DMA Transfer Overview
  152. Memory Map and Registers
  153. Source Address Register (DMA_SARn)
  154. Destination Address Register (DMA_DARn)
  155. DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
  156. DMA Control Register (DMA_DCRn)
  157. Channel Initialization and Startup
  158. Dual-Address Data Transfer Mode
  159. Advanced Data Transfer Controls: Auto-Alignment
  160. Termination
  161. MCG Control 2 Register (MCG_C2)
  162. MCG Control 3 Register (MCG_C3)
  163. MCG Control 6 Register (MCG_C6)
  164. MCG Status and Control Register (MCG_SC)
  165. MCG Auto Trim Compare Value High Register (MCG_ATCVH)
  166. Low Power Bit Usage
  167. External Reference Clock
  168. Initialization / Application information
  169. Using a 32.768 kHz reference
  170. External Crystal / Resonator Connections
  171. External Clock Connections
  172. Memory Map/Register Definitions
  173. OSC Module Modes
  174. Counter
  175. Reset
  176. Glossary
  177. Flash Configuration Field Description
  178. Register Descriptions
  179. Flash Protection
  180. Flash Operation in Low-Power Modes
  181. Flash Reads and Ignored Writes
  182. Margin Read Commands
  183. Flash Command Description
  184. Security
  185. Reset Sequence
  186. Voltage Reference Select
  187. Analog Channel Inputs (ADx)
  188. ADC Status and Control Registers 1 (ADCx_SC1n)
  189. ADC Configuration Register 1 (ADCx_CFG1)
  190. ADC Configuration Register 2 (ADCx_CFG2)
  191. ADC Data Result Register (ADCx_Rn)
  192. Compare Value Registers (ADCx_CVn)
  193. Status and Control Register 2 (ADCx_SC2)
  194. Status and Control Register 3 (ADCx_SC3)
  195. ADC Offset Correction Register (ADCx_OFS)
  196. ADC Plus-Side Gain Register (ADCx_PG)
  197. ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
  198. ADC Plus-Side General Calibration Value Register (ADCx_CLP3)
  199. ADC Plus-Side General Calibration Value Register (ADCx_CLP1)
  200. Voltage reference selection
  201. Conversion control
  202. Automatic compare function
  203. Calibration function
  204. Temperature sensor
  205. MCU wait mode operation
  206. MCU Low-Power Stop mode operation
  207. Initialization information
  208. Sources of error
  209. bit DAC key features
  210. ANMUX key features
  211. CMP block diagram
  212. CMP Control Register 1 (CMPx_CR1)
  213. CMP Filter Period Register (CMPx_FPR)
  214. DAC Control Register (CMPx_DACCR)
  215. MUX Control Register (CMPx_MUXCR)
  216. Power modes
  217. Startup and operation
  218. CMP interrupts
  219. Digital-to-analog converter
  220. Voltage reference source select
  221. TPM Signal Descriptions
  222. TPM_EXTCLK — TPM External Clock
  223. Status and Control (TPMx_SC)
  224. Counter (TPMx_CNT)
  225. Modulo (TPMx_MOD)
  226. Channel (n) Status and Control (TPMx_CnSC)
  227. Channel (n) Value (TPMx_CnV)
  228. Configuration (TPMx_CONF)
  229. Prescaler
  230. Input Capture Mode
  231. Output Compare Mode
  232. Edge-Aligned PWM (EPWM) Mode
  233. Center-Aligned PWM (CPWM) Mode
  234. Registers Updated from Write Buffers
  235. Reset Overview
  236. Memory map/register description
  237. PIT Upper Lifetime Timer Register (PIT_LTMR64H)
  238. Timer Load Value Register (PIT_LDVALn)
  239. Timer Control Register (PIT_TCTRLn)
  240. Timer Flag Register (PIT_TFLGn)
  241. Interrupts
  242. Example configuration for the lifetime timer
  243. LPTMR signal descriptions
  244. Low Power Timer Control Status Register (LPTMRx_CSR)
  245. Low Power Timer Prescale Register (LPTMRx_PSR)
  246. Low Power Timer Compare Register (LPTMRx_CMR)
  247. LPTMR compare
  248. LPTMR hardware trigger
  249. RTC Time Seconds Register (RTC_TSR)
  250. RTC Time Alarm Register (RTC_TAR)
  251. RTC Control Register (RTC_CR)
  252. RTC Status Register (RTC_SR)
  253. RTC Lock Register (RTC_LR)
  254. RTC Interrupt Enable Register (RTC_IER)
  255. Time counter
  256. Time alarm
  257. Update mode
  258. Block Diagrams
  259. SPSCK — SPI Serial Clock
  260. SPI control register 2 (SPIx_C2)
  261. SPI baud rate register (SPIx_BR)
  262. SPI status register (SPIx_S)
  263. SPI data register (SPIx_D)
  264. SPI match register (SPIx_M)
  265. Slave Mode
  266. SPI Transmission by DMA
  267. SPI Clock Formats
  268. SPI Baud Rate Generation
  269. Error Conditions
  270. Low Power Mode Options
  271. Pseudo-Code Example
  272. I2C Address Register 1 (I2Cx_A1)
  273. I2C Frequency Divider register (I2Cx_F)
  274. I2C Control Register 1 (I2Cx_C1)
  275. I2C Status register (I2Cx_S)
  276. I2C Data I/O register (I2Cx_D)
  277. I2C Control Register 2 (I2Cx_C2)
  278. I2C Programmable Input Glitch Filter register (I2Cx_FLT)
  279. I2C Range Address register (I2Cx_RA)
  280. I2C SMBus Control and Status register (I2Cx_SMB)
  281. I2C Address Register 2 (I2Cx_A2)
  282. I2C SCL Low Timeout Register High (I2Cx_SLTH)
  283. I2C protocol
  284. bit address
  285. Address matching
  286. System management bus specification
  287. Resets
  288. Programmable input glitch filter
  289. Address matching wakeup
  290. Register definition
  291. UART Baud Rate Register High (UARTx_BDH)
  292. UART Baud Rate Register Low (UARTx_BDL)
  293. UART Control Register 2 (UARTx_C2)
  294. UART Status Register 1 (UARTx_S1)
  295. UART Status Register 2 (UARTx_S2)
  296. UART Control Register 3 (UARTx_C3)
  297. UART Data Register (UARTx_D)
  298. UART Match Address Registers 1 (UARTx_MA1)
  299. UART Match Address Registers 2 (UARTx_MA2)
  300. UART Control Register 5 (UARTx_C5)
  301. Receiver functional description
  302. Additional UART functions
  303. Interrupts and status flags
  304. Port Data Output Register (GPIOx_PDOR)
  305. Port Toggle Output Register (GPIOx_PTOR)
  306. Port Data Direction Register (GPIOx_PDDR)
  307. Port Data Output Register (FGPIOx_PDOR)
  308. Port Clear Output Register (FGPIOx_PCOR)
  309. Port Data Input Register (FGPIOx_PDIR)
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MKL04Z16VFK4MKL04Z16VFM4MKL04Z16VLC4MKL04Z16VLF4MKL04Z32VFK4MKL04Z32VFM4MKL04Z32VLC4MKL04Z32VLF4MKL04Z8VFK4MKL04Z8VFM4MKL04Z8VLC4
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