The three primary modes of operation are run, wait and stop. The WFI instructioninvokes both wait and stop modes for the chip. The primary modes are augmented in anumber of ways to provide lower power based on application needs.Table 7-1. Chip power modesChip mode Description Core mode NormalrecoverymethodNormal run Allows maximum performance of chip. Default mode out of reset; on-chip voltage regulator is on.Run —Normal Wait -via WFIAllows peripherals to function while the core is in sleep mode, reducingpower. NVIC remains sensitive to interrupts; peripherals continue to beclocked.Sleep InterruptNormal Stop -via WFIPlaces chip in static state. Lowest power mode that retains all registerswhile maintaining LVD protection. NVIC is disabled; AWIC is used towake up from interrupt; peripheral clocks are stopped.Sleep Deep InterruptVLPR (Very LowPower Run)On-chip voltage regulator is in a low power mode that supplies onlyenough power to run the chip at a reduced frequency. Only MCGmodes BLPI and BLPE can be used in VLPR. Reduced frequencyFlash access mode (1 MHz); LVD off; in BLPI clock mode, only the fastinternal reference oscillator is available to provide a low power nominal4MHz source for the core with the nominal bus and flash clock requiredto be <800kHz; alternatively, BLPE clock mode can be used with anexternal clock or the crystal oscillator providing the clock source.Run —VLPW (VeryLow PowerWait) -via WFISame as VLPR but with the core in sleep mode to further reducepower; NVIC remains sensitive to interrupts (FCLK = ON). On-chipvoltage regulator is in a low power mode that supplies only enoughpower to run the chip at a reduced frequency.Sleep InterruptVLPS (Very LowPower Stop)-viaWFIPlaces chip in static state with LVD operation off. Lowest power modewith ADC and pin interrupts functional. Peripheral clocks are stopped,but OSC, LPTMR, RTC, CMP can be used. TPM and UART canoptionally be enabled if their clock source is enabled. NVIC is disabled(FCLK = OFF); AWIC is used to wake up from interrupt. On-chipvoltage regulator is in a low power mode that supplies only enoughpower to run the chip at a reduced frequency. All SRAM is operating(content retained and I/O states held).Sleep Deep InterruptLLS (LowLeakage Stop)State retention power mode. Most peripherals are in state retentionmode (with clocks stopped), but OSC, LLWU, LPTMR, RTC, CMP, canbe used. NVIC is disabled; LLWU is used to wake up.NOTE: The LLWU interrupt must not be masked by the interruptcontroller to avoid a scenario where the system does not fullyexit stop mode on an LLS recovery.All SRAM is operating (content retained and I/O states held).Sleep Deep WakeupInterrupt1VLLS3 (VeryLow LeakageStop3)Most peripherals are disabled (with clocks stopped), but OSC, LLWU,LPTMR, RTC, CMP can be used. NVIC is disabled; LLWU is used towake up.SRAM_U and SRAM_L remain powered on (content retained and I/Ostates held).Sleep Deep Wakeup Reset2Table continues on the next page...Power modesKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012126 Freescale Semiconductor, Inc.
