x x+1 x+2 x+3next5..v_wxyznextwdatanext400v_wxyz 400v_wxyz nextnext5..v_wxyzwdata bfi rdatawdata bfi rdatanextrdataCYCLE RULERhclkBME AHB Input Busmx_haddrmx_hattrmx_hwritemx_hwdatamx_hrdatamx_hreadyBME AHB Output Bussx_haddrsx_hattrsx_hwritesx_hwdatasx_hrdatasx_hreadyBME States + Datapathcontrol_state_dp1control_state_dp2reg_addr_data_dpFigure 17-2. Decorated store: bit field insert timing diagramAll the decorated store operations follow the same execution template shown in the figureabove, a 2-cycle read-modify-write operation:• Cycle x, 1st AHB address phase: Write from input bus (mx_h) is translatedinto a read operation on the output bus (sx_h) using the actual memoryaddress (with the decoration removed) and then captured in a register(reg_addr_data_dp)• Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual)memory address is output (sx_h)• Cycle x+1, 1st AHB data phase: Memory read data (sx_hrdata) is modified using theinput bus write data (mx_hwdata) and the function defined by the decoration andcaptured in a data register (reg_addr_data_dp); the input bus cycle is stalled(mx_hready = 0)• Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the outputwrite data bus (sx_hwdata)Chapter 17 Bit Manipulation Engine (BME)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 243
