WDOGMode ControllerPeripheralbridge 0RegisteraccessFigure 3-13. COP watchdog configurationTable 3-22. Reference links to related informationTopic Related module ReferenceClocking Clock distributionPower management Power managementProgramming model System IntegrationModule (SIM)SIM3.4.10.1 COP clocksThe two clock inputs for the COP are the 1 kHz clock and the bus clock.3.4.10.2 COP watchdog operationThe COP watchdog is intended to force a system reset when the application software failsto execute as expected. To prevent a system reset from the COP timer (when it isenabled), application software must reset the COP counter periodically. If the applicationprogram gets lost and fails to reset the COP counter before it times out, a system reset isgenerated to force the system back to a known starting point.After any reset, the COP watchdog is enabled. If the COP watchdog is not used in anapplication, it can be disabled by clearing COPCTRL[COPT] in the SIM.The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of theSIM's Service COP (SRVCOP) register during the selected timeout period. Writes do notaffect the data in the SRVCOP register. As soon as the write sequence is complete, theCOP timeout period is restarted. If the program fails to perform this restart during thetimeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA iswritten to the SRVCOP register, the microcontroller immediately resets.System ModulesKL04 Sub-Family Reference Manual, Rev. 3.1, November 201262 Freescale Semiconductor, Inc.
