ADC Channel(SC1n[ADCH])Channel Input signal(SC1n[DIFF]= 1)Input signal(SC1n[DIFF]= 0)10101 AD21 Reserved Reserved10110 AD22 Reserved Reserved10111 AD23 Reserved Reserved11000 AD24 Reserved Reserved11001 AD25 Reserved Reserved11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)11011 AD27 Bandgap (Diff)1 Bandgap (S.E)111100 AD28 Reserved Reserved11101 AD29 -VREFH (Diff) VREFH (S.E)11110 AD30 Reserved VREFL11111 AD31 Module Disabled Module Disabled1. This is the PMC bandgap 1V reference voltage. Prior to reading from this ADC channel, ensure that you enable thebandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG)specification.3.7.1.4 ADC Analog Supply and Reference ConnectionsThis device internally connects VDDA to VDD and VSSA to VSS.This device contains separate VREFH and VREFL pins on 32-pin and higher devices.These pins are internally connected to VDD and VSS respectively, on packages less than32-pin.3.7.1.5 ADC Reference OptionsThe ADC supports the following references:• VREFH/VREFL - connected as the primary reference option• VDDA - connected as the VALT reference option3.7.1.6 Alternate clockFor this device, the alternate clock is connected to OSCERCLK.NOTEThis clock option is only usable when OSCERCLK is in theMHz range. A system with OSCERCLK in the kHz range hasthe optional clock source below minimum ADC clock operatingfrequency.AnalogKL04 Sub-Family Reference Manual, Rev. 3.1, November 201274 Freescale Semiconductor, Inc.
