Table 7-2. Module operation in low power modes (continued)Modules VLPR VLPW Stop VLPS LLS VLLSxCore clock 4 MHz max OFF OFF OFF OFF OFFPlatform clock 4 MHz max 4 MHz max OFF OFF OFF OFFSystem clock 4 MHz maxOFF in CPO4 MHz max OFF OFF OFF OFFBus clock 1 MHz maxOFF in CPO1 MHz max OFF24 MHz max inPSTOP2 fromRUN1 MHz max inPSTOP2 fromVLPROFF OFF OFFMemory and memory interfacesFlash 1 MHz maxaccess - noprogramNo registeraccess in CPOlow power low power low power OFF OFFSRAM_U andSRAM_Llow power low power low power low power low power low power inVLLS3, OFF inVLLS0/1Communication interfacesUART0 1 MbpsAsync operationin CPO1 Mbps Async operationFF in PSTOP2Async operation static OFFSPI0 master mode500 kbps,slave mode 250kbpsstatic, slavemode receive inCPOmaster mode500 kbps,slave mode 250kbpsstatic, slavemode receiveFF in PSTOP2static, slavemode receivestatic OFFI2C0 50 kbpsstatic, addressmatch wakeupin CPO50 kbps static, addressmatch wakeupFF in PSTOP2static, addressmatch wakeupstatic OFFTimersTPM FFAsync operationin CPOFF Async operationFF in PSTOP2Async operation static OFFPIT FFstatic in CPOFF static static static OFFLPTMR FF FF Async operationFF in PSTOP2Async operation Async operation Asyncoperation4Table continues on the next page...Chapter 7 Power ManagementKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 129
