Table 3-4. ARM Cortex-M0+ parameter settingsParameter Verilog Name Value DescriptionArch Clock Gating ACG 1 = Present Implements architectural clock gatingDAP Slave Port Support AHBSLV 1 Support any AHB debug access port (like theCM4 DAP)DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM tableEndianess BE 0 Little endian control for data transfersBreakpoints BKPT 2 Implements 2 breakpointsDebug Support DBG 1 = PresentHalt Event Support HALTEV 1 = PresentI/O Port IOP 1 = Present Implements single-cycle ld/st accesses tospecial address spaceIRQ Mask Enable IRQDIS 0x00000000 Assume (for now) all 32 IRQs are used (set ifIRQ is disabled)Debug Port Protocol JTAGnSW 0 = SWD SWD protocol, not JTAGCore Memory Protection MPU 0 = Absent No MPUNumber of IRQs NUMIRQ 32 Assume full NVIC request vectorReset all regs RAR 0 = Standard Do not force all registers to be async resetMultiplier SMUL 0 = Fast Mul Implements single-cycle multiplierMulti-drop Support SWMD 0 = Absent Do not include serial wire support for multi-dropSystem Tick Timer SYST 1 = Present Implements system tick timer (for CM4compatibility)DAP Target ID TARGETID 0User/Privileged USER 1 = Present Implements processor operating modesVector Table Offset Register VTOR 1 = Present Implements relocation of exception vectortableWIC Support WIC 1 = Present Implements WIC interfaceWIC Requests WICLINES 34 Exact number of wakeup IRQs is 34Watchpoints WPT 2 Implements 2 watchpointsFor details on the ARM Cortex-M0+ processor core, see the ARM website:www.arm.com.3.3.1.2 Buses, Interconnects, and InterfacesThe ARM Cortex-M0+ core has two bus interfaces:• single 32-bit AMBA-3 AHB-Lite system interface that provides connections toperipherals and all system memory, which includes flash and RAM.• single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores.Chapter 3 Chip ConfigurationKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 45
