NXP Semiconductors MCF5253 manuals
MCF5253
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- MCF5253 Reference Manual,
- about this book
- revision history
- register summary
- MCF5253 Overview
- MCF5253 Block Diagram
- MCF5253 Feature Details
- MCF5253 Functional Overview
- Instruction Cache
- ATA Controller
- CD-ROM Encoder/Decoder
- Timer Module
- GPIO Interface
- Sleep and Wake-Up Modes
- Overview
- GPIO
- Read-Write Control
- Chip Selects
- Serial Module Signals
- Digital Audio Interface Signals
- Subcode Interface
- Queued Serial Peripheral Interface (QSPI)
- USB Controller
- Test Mode
- BDM/JTAG Signals
- On-Chip Linear Regulator
- Processor Pipelines
- ColdFire Processor Memory Map and Register Definitions
- Address Registers (A0–A6)
- Description
- Supervisor Memory Map and Register Description
- Vector Base Register (VBR)
- Exception Stack Frame Definition
- Processor Exceptions
- Address Error Exception
- Debug Interrupt
- Fault-on-Fault Halt
- MOVE Instruction Execution Times
- Standard One Operand Instruction Execution Times
- Miscellaneous Instruction Execution Times
- Branch Instruction Execution Times
- PLL Features
- PLL Memory Map and Register Definitions
- PLL Operation
- Dynamic Clock Switching
- Reduced Power Mode
- Enter Sleep Mode
- Instruction Cache Features
- Instruction Cache Physical Organization
- Memory Reference Attributes
- Instruction Cache Memory Map and Register Definitions
- Instruction Cache Register
- Access Control Registers
- SRAM Features
- SRAM Initialization
- SDRAM Features
- Synchronous Operation
- DRAM Controller Signals in Synchronous Mode
- DRAM Controller Registers
- DRAM Address and Control (DACR0) (Synchronous Mode)
- DRAM Controller Mask Registers (DMR0)
- General Synchronous Operation Guidelines
- Interfacing Example
- Continuous Page Mode
- Auto-Refresh Operation
- Self-Refresh Operation
- Initialization Sequence
- SDRAM Example
- SDRAM Interface Configuration
- DACR Initialization
- DMR Initialization
- Mode Register Initialization
- Initialization Code
- Bus Features
- Address Bus
- Reset In
- Bus Cycle Execution
- Read Cycle
- Write Cycle
- Back-to-Back Bus Cycles
- Burst Cycles
- Misaligned Operands
- Reset Operation
- Software Watchdog Reset
- SIM Overview
- SIM Register Memory Map
- SIM Module Programming Registers
- Device ID Register
- Primary Interrupt Controller Registers
- Interrupt Mask Register
- Secondary Interrupt Controller Registers
- Interrupt Level Selection
- Spurious Vector Register
- Software Interrupts
- System Protection and Reset Status Registers
- System Protection Control Register
- Software Watchdog Interrupt Vector Register
- Software Watchdog Service Register
- Internal Arbitration Operation
- PARK Register Bit Configuration
- General Purpose I/Os
- General Purpose Inputs
- General Purpose Input Interrupts
- General Purpose Outputs
- Multiplexed Pin Configuration
- Chip Select Features
- CS1/QSPI_CS3/GPIO28
- Chip Select Operation
- Global Chip-Select Operation
- Chip Select Module Registers
- Chip Select Mask Register
- Chip Select Control Register
- Code Example
- Timer Module Overview
- Timer Signal Output
- Configuring the Timer for Output Mode (TIMER0)
- Timer Reference Registers (TRR0, TRR1)
- Timer Counters (TCN0, TCN1)
- Timer Initialization Example Code
- ADC Memory Map and Register Definitions
- AD Value Register (ADvalue)
- Functional Description
- IDE and SmartMedia Overview
- Buffer Enables BUFENB1, BUFENB2, and Associated Logic
- Generation of IDE_DIOR and IDE_DIOW
- Cycle Termination on CS2 (IDE_DIOR, IDE_DIOW)
- SmartMedia Interface Setup
- SmartMedia Timing
- Setting Up The IDE Interface
- IDE Timing Diagram
- Flash Media Interface
- Flash Media Interface Memory Map and Register Definitions
- Flash Media Interface Operation
- Flash Media Command Registers in Memory Stick Mode
- Flash Media Command Register 2 in Secure Digital Mode
- Flash Media Data Registers
- Flash Media Status Register
- Flash Media Interface Operation in Memory Stick Mode
- Reading Data from the Memory Stick
- Writing Data to the Memory Stick
- Interrupt from Memory Stick
- Send Command to Card
- Write Data to Card
- Commonly Used Commands in SD Mode
- Send Command to Card (Receive Multiple Data Blocks and Status)
- Send Command to Card (Write Multiple Data Blocks)
- DMA Features
- DMA Request
- DMA Module Overview
- DMA Memory Map and Register Definitions
- Source Address Register
- Destination Address Register
- Byte Count Register
- DMA Control Register
- DMA Status Register
- DMA Interrupt Vector Register
- Transfer Request Generation
- Dual-Address Write
- Channel Prioritization
- Data Transfer
- Channel Termination
- UART Module Features
- Serial Communication Channel
- UART Module Signal Definitions
- Request-To-Send
- Baud-Rate Generator/Timer
- Transmitter
- Receiver
- Receiver FIFO
- Looping Modes
- Local Loopback Mode
- Multidrop Mode
- Bus Operation
- Mode Register 1 (UMR1n)
- Mode Register 2 (UMR2n)
- Status Registers (USRn)
- Clock-Select Registers (USCRn)
- Command Registers (UCRn)
- Reset Transmitter
- Transmitter Enable
- Receiver Buffer Registers (UBRn)
- Input Port Change Registers (UIPCRn)
- Interrupt Status Registers (UISRn)
- Interrupt Mask Registers (UIMRn)
- Baud Rate Generator (MSB) Register (UBG1n)
- Output Port Data Registers (UOP1n)
- Programming
- UART Module Initialization Sequence
- Features
- Internal Bus Interface
- QSPI RAM
- Transmit RAM
- Baud Rate Selection
- Transfer Length
- QSPI Memory Map and Register Definitions
- QSPI Delay Register (QDLYR)
- QSPI Interrupt Register (QIR)
- QSPI Address Register (QAR)
- Command RAM Registers (QCR0–QCR15)
- Programming Example
- Audio Interface Overview
- Audio Interface Block Diagram
- Audio Interface Structure
- Audio Interface Memory Map and Register Definitions
- Audio Interrupt Mask and Status Register Descriptions
- IIS/EIAJ Transmitter Descriptions
- IIS/EIAJ Transmitter Interrupts
- Digital Audio Interface (EBU/SPDIF) Register Descriptions
- IEC958 Receive Interface
- Control Channel Interrupt (IEC958 "C" Channel New Frame)
- EBU Extracted Clock
- U and Q Receive Register Interrupts
- Behavior of User Channel Receive Interface (non-CD data)
- Transmit "C" Channel
- CD Subcode Interrupts
- Free Running Counter Synchronization
- Data Exchange Register Descriptions
- Data Exchange Register Overview
- Data In Selection
- PDIR and PDOR Field Formatting
- Overrun and Underrun with PDIR and PDOR Registers
- audioGlob Register Descriptions
- Audio Interrupts
- PDOR1, PDOR2, and PDOR3 Interrupts
- Audio Interrupt Routines and Timing
- CD-ROM Block Encoder and Decoder Register Descriptions
- CD-ROM Decoder Interrupts
- CD-ROM Encoder Interrupts
- Phase/Frequency Determination and XTRIM Function
- Filtering for the Discrete Time Oscillator
- XTRIM Internal Logic
- START Signal
- Repeated START Signal
- Handshaking
- Generation of START
- Post-Transfer Software Response
- Generation of Repeated START
- Arbitration Lost
- Boot ROM Operation
- Boot Type Detection
- Serial Boot Data Format
- Supported Commands
- Boot from UART
- Creating Appropriate Boot Record Files
- Debug Support Signals
- Breakpoint (BKPT)
- Processor Status Clock (PSTCLK)
- Processor Status Signal Encoding
- Begin Execution of Taken Branch (PST = )
- Begin Execution of RTE Instruction (PST = )
- CPU Halt
- BDM Serial Interface
- Receive Packet Format
- BDM Command Set
- Command Sequence Diagram
- Command Set Descriptions
- Write Address/Data Register (WAREG and WDREG)
- Write Memory Location (WRITE)
- Dump Memory Block (DUMP)
- Fill Memory Block (FILL)
- Resume Execution (GO)
- Read Control Register (RCREG)
- Write Control Register (WCREG)
- Read Debug Module Register (RDMREG)
- Unassigned Opcodes
- Real-Time Debug Support
- Theory of Operation
- Emulator Mode
- Debug Module Hardware
- Address Breakpoint Registers
- Address Attribute Trigger Register
- Program Counter Breakpoint Register (PBR, PBMR)
- Data Breakpoint Registers (DBR, DBMR)
- Trigger Definition Register (TDR)
- Configuration/Status Register (CSR)
- BDM Address Attribute Register (BAAR)
- Freescale-Recommended BDM Pinout
- JTAG Signal Descriptions
- Test Clock (TCK)
- Test Data Input/Development Serial Input (TDI/DSI)
- JTAG Register Definitions
- SAMPLE/PRELOAD Instruction
- BYPASS Instruction
- JTAG Boundary Scan Register
- Obtaining the IEEE 1149.1A Standard
- Introduction
- ATA DMA Address Register (ATA_DADDR)
- USB/FlexCAN Clock Register (USBCANCLK)
- Endianness Issues
- Modes of Operation
- External Signal Description
- ATA_DIOR (Out)
- Timing on ATA Bus
- PIO Mode Timing
- Timing in Multiword DMA Mode
- UDMA In Timing Diagrams
- UDMA Out Timing Diagrams
- Memory Map and Register Definitions
- Memory Map
- Register Descriptions
- Timing Registers
- TIME_1 Register
- TIME_AX Register
- TIME_M Register
- TIME_K Register
- TIME_ZAH Register
- TIME_DZFS Register
- TIME_CYC Register
- FIFO_FILL Register
- Interrupt Registers
- Interrupt_Pending Register
- Interrupt_Enable Register
- Interrupt_Clear Register
- Drive Registers Connected to ATA Bus
- Resetting ATA Bus
- Using DMA Mode to Receive Data from ATA Bus
- Using DMA Mode to Transmit Data to ATA Bus
- Block Diagram
- System Clock
- Module Identification Registers
- General Hardware Parameters (HWGENERAL) Register
- Host Hardware Parameters (HWHOST) Register
- Transmit Buffer Hardware Parameters (HWTXBUF) Register
- Receive Buffer Hardware Parameters (HWRXBUF) Register
- Capability Registers
- Host Controller Structural Parameters (HCSPARAMS)
- Device Controller Interface Version (DCIVERSION)
- Operational Registers
- USB Status Register (USBSTS)
- USB Interrupt Enable Register (USBINTR)
- Frame Index Register (FRINDEX)
- Control Data Structure Segment Register (CTRLDSSEGMENT)
- Device Address Register (DEVICEADDR), Non-EHCI
- Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI
- Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI
- Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
- Configure Flag Register (CONFIGFLAG)
- On-The-Go Status and Control (OTGSC), Non-EHCI
- USB Mode Register (USBMODE)—Non-EHCI
- Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
- Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI
- Endpoint Flush Register (ENDPTFLUSH), Non-EHCI
- Endpoint Status Register (ENDPTSTATUS), Non-EHCI
- Endpoint Complete Register (ENDPTCOMPLETE), Non-EHCI
- Endpoint Control Register n (ENDPTCTRLn), Non-EHCI
- FIFO RAM Controller
- Periodic Frame List
- Asynchronous List Queue Head Pointer
- Isochronous (High-Speed) Transfer Descriptor (iTD)
- iTD Transaction Status and Control List
- iTD Buffer Page Pointer List (Plus)
- Split Transaction Isochronous Transfer Descriptor (siTD)
- siTD Endpoint Capabilities/Characteristics
- siTD Transfer State
- siTD Buffer Pointer List (Plus)
- siTD Back Link Pointer
- Next qTD Pointer
- qTD Token
- qTD Buffer Page Pointer List
- Queue Head Horizontal Link Pointer
- Transfer Overlay
- Periodic Frame Span Traversal Node (FSTN)
- FTSN Normal Path Pointer
- Host Controller Initialization
- Power Port
- Port Suspend/Resume
- Schedule Traversal Rules
- Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
- Periodic Schedule
- Managing Isochronous Transfers Using iTDs
- Software Operational Model for iTDs
- Periodic Scheduling Threshold
- Asynchronous Schedule
- Adding Queue Heads to Asynchronous Schedule
- Removing Queue Heads from Asynchronous Schedule
- Empty Asynchronous Schedule Detection
- Asynchronous Schedule Traversal: Start Event
- Buffer Pointer List Use for Data Streaming with qTDs
- Adding Interrupt Queue Heads to the Periodic Schedule
- Ping Control
- Split Transactions
- Asynchronous—Do-Start-Split
- Split Transaction Interrupt
- Host Controller Operational Model for FSTNs
- Software Operational Model for FSTNs
- Tracking Split Transaction Progress for Interrupt Transfers
- Periodic Interrupt—Do-Start-Split
- Periodic Interrupt—Do-Complete-Split
- Managing the QH[FrameTag] Field
- Rebalancing the Periodic Schedule
- Split Transaction Scheduling Mechanisms for Isochronous
- Tracking Split Transaction Progress for Isochronous Transfers
- Split Transaction Execution State Machine for Isochronous
- Periodic Isochronous—Do Complete Split
- Complete-Split for Scheduling Boundary Cases 2a, 2b
- Split Transaction for Isochronous—Processing Examples
- Port Test Modes
- Interrupts
- Transfer/Transaction Based Interrupts
- Data Buffer Error
- USB Interrupt (Interrupt on Completion (IOC))
- Host System Error
- Endpoint Queue Head
- Endpoint Capabilities/Characteristics
- Endpoint Transfer Descriptor (dTD)
- Device Operational Model
- Port State and Control
- Bus Reset
- Suspend/Resume
- Managing Endpoints
- Stalling
- Data Toggle Inhibit
- Priming Receive Endpoints
- Interrupt/Bulk Endpoint Bus Response Matrix
- Control Endpoint Operation Model
- Status Phase
- Isochronous Endpoint Operational Model
- Isochronous Pipe Synchronization
- Managing Queue Heads
- Queue Head Initialization
- Operational Model For Setup Transfers
- Building a Transfer Descriptor
- Transfer Completion
- Flushing/De-Priming an Endpoint
- Servicing Interrupts
- Deviations from the EHCI Specifications
- Discovery
- Operational Model
- Asynchronous Transaction Scheduling and Buffer Management
- Multiple Transaction Translators
- Embedded Design
- Port Speed Detection
- The CAN System
- Module Disabled Mode
- Listen-only Mode
- FlexCAN Configuration Register (CANMCRn)
- FlexCAN Control Register (CANCTRLn)
- FlexCAN Free Running Timer Register (TIMERn)
- FlexCAN Error Counter Register (ERRCNTn)
- FlexCAN Error and Status Register (ERRSTATn)
- Interrupt Mask Register (IMASKn)
- Message Buffer Structure
- Functional Overview
- Arbitration Process
- Self-Received Frames
- Matching Process
- Locking and Releasing Message Buffers
- CAN Protocol Related Frames
- Time Stamp
- FlexCAN Initialization Sequence
- Miscellaneous Configuration Register (MISCCR)
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