Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-74 Freescale Semiconductor24.9.7 Periodic ScheduleThe periodic schedule traversal is enabled or disabled via the Periodic Schedule Enable bit in theUSBCMD register. If the Periodic Schedule Enable bit is cleared, then the host controller simply does nottry to access the periodic frame list via the PERIODICLISTBASE register. Likewise, when the PeriodicSchedule Enable bit is a one, then the host controller does use the PERIODICLISTBASE register totraverse the periodic schedule. The host controller will not react to modifications to the Periodic ScheduleEnable immediately. In order to eliminate conflicts with split transactions, the host controller evaluates thePeriodic Schedule Enable bit only when FRINDEX[2:0] is zero. The system software must not disable theperiodic schedule if the schedule contains an active split transaction work item that spans the 0b000micro-frame. These work items must be removed from the schedule before the Periodic Schedule Enablebit is cleared. The Periodic Schedule Status bit in the USBSTS register indicates status of the periodicschedule. The system software enables (or disables) the periodic schedule by setting (or clearing) thePeriodic Schedule Enable bit in the USBCMD register. The software then can poll the Periodic ScheduleStatus bit to determine when the periodic schedule has made the desired transition. The software must notmodify the Periodic Schedule Enable bit unless the value of the Periodic Schedule Enable bit equals thatof the Periodic Schedule Status bit.The periodic schedule is used to manage all isochronous and interrupt transfer streams. The base of theperiodic schedule is the periodic frame list. The software links schedule data structures to the periodicframe list to produce a graph of scheduled data structures. The graph represents an appropriate sequenceof transactions on the USB. Figure 24-47 illustrates isochronous transfers (using iTDs and siTDs) with aperiod of one are linked directly to the periodic frame list. Interrupt transfers (are managed with queueheads) and isochronous streams with periods other than one are linked following the period-oneiTD/siTDs. Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates arelinked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queueheads with a poll rate of one, on the very end.Table 24-64. Operation of FRINDEX and SOFV (SOF Value Register)Current NextFRINDEX[13:3] SOFV FRINDEX[2:0] FRINDEX[13:3] SOFV FRINDEX[2:0]N N 111 N+1 N 000N+1 N 000 N+1 N+1 001N+1 N+1 001 N+1 N+1 010N+1 N+1 010 N+1 N+1 011N+1 N+1 011 N+1 N+1 100N+1 N+1 100 N+1 N+1 101N+1 N+1 101 N+1 N+1 110N+1 N+1 110 N+1 N+1 111
