Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-116 Freescale SemiconductorPointer field of each siTD references the appropriate siTD data structure (and the Back Pointer T-bits arecleared).The initial SplitXState of the first siTD is Do Start Split. The host controller will visit the first siTD eighttimes during frame X. The C-mask bits in micro-frames 0 and 1 are ignored because the state is Do StartSplit. During micro-frame 4, the host controller determines that it can run a start-split (and does) andchanges SplitXState to Do Complete Split. During micro-frames 6 and 7, the host controller executescomplete-splits. Notice the siTD for frame X+1 has it's SplitXState initialized to Do Complete Split. Asthe host controller continues to traverse the schedule during H-Frame X+1, it will visit the second siTDeight times. During micro-frames 0 and 1 it will detect that it must execute complete-splits.During H-Frame X+1, micro-frame 0, the host controller detects that siTDX+1 's Back Pointer[T] bit is azero, saves the state of siTD X+1 and fetches siTDX. It executes the complete split transaction using thetransaction state of siTD X. If the siTD X split transaction is complete, siTD's Active bit is cleared andresults written back to siTDX . The host controller retains the fact that siTDX is retired and transitions theSplitXState in siTDX+1 to Do Start Split. At this point, the host controller is prepared to execute thestart-split for siTDX+1 when it reaches micro-frame 4. If the split-transaction completes early(transaction-complete is defined in Section 24.9.12.3.5, “Periodic Isochronous—Do Complete Split”),that is, before all the scheduled complete-splits have been executed, the host controller changessiTD X[SplitXState] to Do Start Split early and naturally skips the remaining scheduled complete-splittransactions. For this example, siTDX+1 does not receive a DATA0 response until H-Frame X+2,micro-frame 1.During H-Frame X+2, micro-frame 0, the host controller detects that siTDX+2 's Back Pointer[T] bit is zero,saves the state of siTDX+2 and fetches siTD X+1 . As described above, it executes another split transaction,receives an MDATA response, updates the transfer state, but does not modify the Active bit. The hostcontroller returns to the context of siTDX+2 , and traverses it's next pointer without any state change updatesto siTDX+2 .During H-Frame X+2, micro-frame 1, the host controller detects siTD X+2 's S-mask[0] bit is zero, savesthe state of siTD X+2 and fetches siTDX+1 . It executes another complete-split transaction, receives aDATA0 response, updates the transfer state and clears the Active bit. It returns to the state of siTDX+2 andchanges its SplitXState to Do Start Split. At this point, the host controller is prepared to execute start-splitsfor siTD X+2 when it reaches micro-frame 4.24.9.13 Port Test ModesEHCI host controllers implement the port test modes Test J_State, Test K_State, Test_Packet, TestForce_Enable, and Test SE0_NAK as described in the USB Specification Revision 2.0. The required, porttest sequence is (assuming the CF-bit in the CONFIGFLAG register is set):• Disable the periodic and asynchronous schedules by clearing the Asynchronous Schedule Enableand Periodic Schedule Enable bits in the USBCMD register.• Place all enabled root ports into the suspended state by setting the Suspend bit in each appropriatePORTSC register.• Clear the Run/Stop bit in the USBCMD register and wait for the HCHalted bit in the USBSTSregister, to transition to a one. Note that an EHCI host controller implementation may optionally
