Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-18 Freescale Semiconductor24.6.3.2 USB Status Register (USBSTS)The USB status register indicates various states of each module and any pending interrupts. This registerdoes not indicate status resulting from a transaction on the serial bus. The software clears certain bits inthis register by writing a 1 to them (indicated by a W1C in the bit’s W cell in the figure).Address MBAR2 0x744 Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R AS PS RCL HCH SLI SRI URI AAI SEI FRI PCI UEI UIW W1C W1C W1C W1C W1C W1C W1C W1C W1CReset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0Figure 24-15. USB Status Register (USBSTS) RegisterTable 24-16. USB Status Register (USBSTS) Register Field DescriptionsField Description31–16 Reserved.15ASAsynchronous Schedule Status. This bit reports the current real status of the Asynchronous Schedule. Thecontroller is not required to immediately disable or enable the Asynchronous Schedule when the softwaretransitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and theAsynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) ordisabled (0). Used only in host mode.1 Enabled.0 Disabled.14PSPeriodic Schedule Status. This bit reports the current real status of the Periodic Schedule. The controller is notrequired to immediately disable or enable the Periodic Schedule when the software transitions the PeriodicSchedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the samevalue, the Periodic Scheduleis either enabled (1) or disabled (0). Used only in host mode.1 Enabled.0 Disabled.13RCLReclamation. This is a status bit used to detect an empty asynchronous schedule. Used only in host mode.1 Empty asynchronous schedule.0 Non-empty asynchronous schedule.12HCHHCHaIted. This bit is a zero whenever the Run/Stop bit is a one. The controller sets this bit to one after it hasstopped executing because of the Run/Stop bit being set to 0, either by the software or by the Host Controllerhardware (for example, internal error). Used only in host mode.1 Halted.0 Running.11–9 Reserved.
