Synchronous DRAM Controller ModuleMCF5253 Reference Manual, Rev. 17-16 Freescale Semiconductor7.5 Initialization SequenceSynchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports thissequence with the following procedure:1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before anyaction is taken on the SDRAMs. This is normally around 100 μs.2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable PALL orREF commands.3. Issue a PALL command to the SDRAMs by setting DCR[IP] and accessing a SDRAM location.Wait the time (determined by tRP ) before any other execution.4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.5. Before issuing the MRS command, determine if the DMR mask bits need to be modified to allowthe MRS to execute properly.6. Issue the MRS command by setting DACR[IMRS] and accessing a location in the SDRAM.NOTEMode register settings are driven on the SDRAM address bus, so care mustbe taken to change DMR[BAM] if the mode register configuration does notfall in the address range determined by the address mask bits. After themode register is set, DMR mask bits can be restored to their desiredconfiguration.7.5.1 Mode Register SettingsIt is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency,through the SDRAM mode register. CAS latency is a function of the speed of the SDRAM and the busclock of the DRAM controller. The DRAM controller operates at a CAS latency of 1 or 2.Although the MCF5253 DRAM controller supports bursting operations, it does not use the burstingfeatures of the SDRAMs. Because the MCF5253 can burst operand sizes of 1, 2, 4, or 16 bytes long, theconcept of a fixed burst length in the SDRAMs mode register becomes problematic. Therefore, theMCF5253 DRAM controller generates the burst cycles rather than the SDRAM device. Because theMCF5253 generates a new address and a READ or WRITE command for each transfer within the burst, theSDRAM mode register should be set either to a burst length of one or to not burst. This allows bursting tobe controlled by the MCF5253 instead.The SDRAM mode register is written to by setting the associated block’s DACR[IMRS]. First, the baseaddress and mask registers must be set to the appropriate configuration to allow the mode register to be set.NOTEImproperly set DMR mask bits may prevent access to the mode registeraddress. Thus, the user should determine the mapping of the mode registeraddress to the MCF5253 address bits to find out if an access is blocked. Ifthe DMR setting prohibits mode register access, the DMR should bereconfigured to enable the access and then set to its necessary configurationafter the MRS command executes.
