Bus OperationMCF5253 Reference Manual, Rev. 18-14 Freescale SemiconductorThe MCF5253 converts misaligned operand accesses that are noncachable to a sequence of alignedaccesses. Figure 8-14 illustrates the transfer of a longword operand from a byte address to a 32-bit port,requiring more than one bus cycle. The slave device supplies the byte and acknowledges the data transfer.The next two bytes are transferred during the second cycle. During the third cycle, the byte offset is now$0; the port supplies the final byte and the operation is complete. Figure 8-14 is similar to the exampleillustrated in Figure 8-15 except that the operand is word-sized and the transfer requires only two buscycles.Figure 8-14. Misaligned Longword TransferFigure 8-15. Misaligned Word Transfer8.7 Reset OperationThe MCF5253 processor supports one type of reset which resets the entire MCF5253: the external masterreset input (RSTI).To perform a master reset, an external device asserts the reset input pin (RSTI). When power is applied tothe system, external circuitry should assert RSTI for a minimum of 16 CRIN cycles after Vcc is withintolerance. Figure 8-16 is a functional timing diagram of the master reset operation, illustratingrelationships among VDD, RSTI, mode selects, and bus signals. The crystal oscillation on CRIN, CROUTmust be stable by the time VDD reaches the minimum operating specification. The crystal should startoscillating as V DD is ramped up to clear out contention internal to the MCF5253 processor caused by therandom states of internal flip-flops on power up. RSTI is internally synchronized for two CRIN cyclesbefore being used and must meet the specified setup and hold times in relationship to CRIN to berecognized.TRANSFER 1TRANSFER 2TRANSFER 3––OP 0OP 3–––OP 2––OP 1–31 24 23 16 15 8 7 0TRANSFER 1TRANSFER 2–OP 0––––OP 1–31 24 23 16 15 8 7 0
