Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-134 Freescale Semiconductor24.11.3.2.2 Data Toggle InhibitThis feature is for test purposes only and should never be used during normal device controller operation.Setting the data toggle Inhibit bit active ('1') causes the USB_DR to ignore the data toggle pattern that isnormally sent and accept all incoming data packets regardless of the data toggle state.In normal operation, the USB_DR checks the DATA0/DATA1 bit against the data toggle to determine ifthe packet is valid. If Data PID does not match the data toggle state bit maintained by the device controllerfor that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the devicecontroller assumes the packet was already received and discards the packet (not reporting it to the DCD).To prevent the USB_DR from re-sending the same packet, the device controller will respond to the errorpacket by acknowledging it with either an ACK or NYET response.24.11.3.3 Device Operational Model For Packet TransfersAll transactions on the USB bus are initiated by the host and in turn, the device must respond to any requestfrom the host within the turnaround time stated in the USB 2.0 Specification.A USB host will send requests to the USB_DR in an order that can not be precisely predicted as a singlepipeline, so it is not possible to prepare a single packet for the device controller to execute. However, theorder of packet requests is predictable when the endpoint number and direction is considered. For example,if endpoint 3 (transmit direction) is configured as a bulk pipe, then we can expect the host will send INrequests to that endpoint. This USB_DR prepares packets for each endpoint/direction in anticipation of thehost request. The process of preparing the device controller to send or receive data in response to hostinitiated transaction on the bus is referred to as ‘priming’ the endpoint. This term will be used throughoutthe following documentation to describe the USB_DR operation so the DCD can be architected properlyuse priming. Further, note that the term ‘flushing’ is used to describe the action of clearing a packet thatwas queued for execution.24.11.3.3.1 Priming Transmit EndpointsPriming a transmit endpoint will cause the device controller to fetch the device transfer descriptor (dTD)for the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it will be storedin the dQH until the device controller completes the transfer described by the dTD. Storing the dTD in thedQH allows the device controller to fetch the operating context needed to handle a request from the hostwithout the need to follow the linked list, starting at the dQH when the host request is received.After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the devicecontroller. This FIFO is split into virtual channels so that the leading data can be stored for any endpointup to the maximum number of endpoints configured at device synthesis time.After a priming request is complete, an endpoint state of primed is indicated in the ENDPTSTATUSregister. For a primed transmit endpoint, the device controller can respond to an IN request from the hostand meet the stringent bus turnaround time of High Speed USB.Since only the leading data is stored in the device controller FIFO, it is necessary for the device controllerto begin filling in behind leading data after the transaction starts. The FIFO must be sized to account forthe maximum latency that can be incurred by the system memory bus.
