System Integration Module (SIM)MCF5253 Reference Manual, Rev. 19-24 Freescale SemiconductorNOTEWhen using the park on current master setting, the first master to arbitratefor the bus becomes the current master. The corresponding priority schemeshould be interpreted as the priority of the next master once the currentmaster finishes.9.8 General Purpose I/O SThe MCF5253 has up to 57 programmable general-purpose outputs and up to 60 programmablegeneral-purpose inputs. Two groups of 32-bit registers control these GPIOs.Table 9-25. Park Bit DescriptionsBit Name DescriptionIARBCTRL Legacy bit.0 Normal use1 do not useEARBCTRL Legacy bit.0 Normal use1 do not useSHOWDATA Not usedBCR24BIT This bit controls the BCR and address mapping for the DMA. The bit allows the byte count register to be usedas a 24-bit register. See Section 14.4, “DMA Memory Map and Register Definitions” for memory maps and bitpositions for the BCRs.0 DMA BCRs function as 16-bit counters.1 DMA BCRs function as 24-bit counters.Table 9-26. General Purpose I/OAddress Name Width Description Reset Value AccessMBAR2 + $0x000 GPIO-READ 32 gpio input value RMBAR2 + $0x004 GPIO-OUT 32 gpio output value 0 R/WMBAR2 + $0x008 GPIO-EN 32 output enable 0 R/WMBAR2 + $0x00C GPIO-FUNCTION 32 function select 0 R/WMBAR2 + $0x0B0 GPIO1-READ 32 gpio input value – RMBAR2 + $0x0B4 GPIO1-OUT 32 gpio output value 0 R/WMBAR2 + $0x0B8 GPIO1-EN 32 output enable 0 R/WMBAR2 + $0x0BC GPIO1-FUNCTION 32 function select 0 R/WMBAR2 + $0x0C0 GPIO-INT-STAT 32 interrupt status – RMBAR2 + $0x0C0 GPIO-INT-CLEAR 32 interrupt clear – WMBAR2 + $0x0C4 GPIO-INT-EN 32 interrupt enable 0 R/W
