MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 6-1Chapter 6Static RAM (SRAM)This chapter describes the SRAM operation, memory map, register descriptions, initialization and SRAMpower management.6.1 SRAM Features• Two 64 Kbyte SRAMS• Single-cycle access• Physically located on processor's high-speed local bus• Memory location programmable on any 64 Kbyte address boundary• Byte, word, longword address capabilities6.2 SRAM OperationThe SRAM module provides a general-purpose memory block that the ColdFire processor can access in asingle cycle. The location of the memory block can be specified to any modulo-64K address within the4GB address space. The memory is ideal for storing critical code or data structures or for use as the systemstack. Because the SRAM module is physically connected to the processor's high-speed local bus.Depending on configuration information, instruction fetches may be sent to both the cache and the SRAMblock simultaneously. If the reference is mapped into the region defined by the SRAM, the SRAMprovides the data back to the processor, and the cache data discarded. Accesses from the SRAM moduleare not cached.Only SRAM1 can be accessed by the DMA controller of the MCF5253. SRAM0 and SRAM1 are madeup of two memory arrays each consisting of 2048 lines, with 16 Bytes in each line.As SRAM1 can be accessed by the DMA then the split in the array (Upper 32K bank and Lower 32K bank)allows simultaneous access by both DMA and the CPU. Figure 1-1 shows this concept.6.3 SRAM Memory Map and Register DefinitionsThe SRAM programming model includes a description of the SRAM base address register (RAMBAR),SRAM initialization, and power management.6.3.1 SRAM Base Address RegisterThe configuration information in the SRAM Base Address Register (RAMBAR[0:1]) controls theoperation of the SRAM module.• There are 2 RAMBAR registers. One for SRAM0, the second for SRAM1.
