Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-128 Freescale SemiconductorRecommended: enable all device interrupts including: USBINT, USBERRINT, Port ChangeDetect, USB Reset Received, DCSuspend.For a list of available interrupts refer to USBINTR register description Table 24-17 and theUSBSTS register description Table 24-16.6. Set Run/Stop bit to Run Mode.After the Run bit is set, a device reset will occur. The DCD must monitor the reset event and setthe DEVICEADDR register, set the ENDPTCTRLx registers, and adjust the software state asdescribed in Section 24.11.2.1, “Bus Reset.NOTEEndpoint 0 is designed as a control endpoint only and does not need to beconfigured using ENDPTCTRL0 register.It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setuppacket. The contents of the first setup packet will require a response in accordance with the USB 2.0Specification, Chapter 9, Device Framework, command set.24.11.2 Port State and ControlFrom a chip or system reset, the USB_DR enters the powered state. A transition from the powered state tothe attach state occurs when the Run/Stop bit is set to a '1'. After receiving a reset on the bus, the port willenter the defaultFS or defaultHS state in accordance with the protocol reset described in Appendix C.2 ofthe USB Specification Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device.
