Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 24-10324.9.12.2.9 Rebalancing the Periodic ScheduleThe system software must occasionally adjust a periodic queue head's S-mask and C-mask fields duringoperation. This need occurs when adjustments to the periodic schedule create a new bandwidth budget andone or more queue head's are assigned new execution footprints (that is, new S-mask and C-mask values).It is imperative that the system software must not update these masks to new values in the midst of a splittransaction. In order to avoid any race conditions with the update, the host controller provides a simpleassist to the system software. The system software sets the Inactivate-on-next-Transaction (I) bit to signalthe host controller that it intends to update the S-mask and C-mask on this queue head. The systemsoftware then waits for the host controller to observe the I-bit is set and transitions the Active bit to a zero.The rules for how and when the host controller clears the Active bit are:• If the Active bit is cleared, no action is taken. The host controller does not attempt to advance thequeue when the I-bit is set.• If the Active bit is set and the SplitXState is DoStart (regardless of the value of S-mask), the hostcontroller simply clears the Active bit. The host controller is not required to write the transfer stateback to the current qTD. Note that if the S-mask indicates that a start-split is scheduled for thecurrent micro-frame, the host controller must not issue the start-split bus transaction; it must clearthe Active bit.The system software must save transfer state before setting the I-bit. This is required so that it can correctlydetermine what transfer progress (if any) occurred after the I-bit was set and the host controller executedit's final bus-transaction and cleared the Active bit.After the system software has updated the S-mask and C-mask, it must then reactivate the queue head.Since the Active bit and the I-bit cannot be updated with the same write, the system software needs to usethe following algorithm to coherently re-activate a queue head that has been stopped using the I-bit.1. Set the Halted bit, then2. Clear the I-bit, then3. Set the Active bit and clear the Halted bit in the same write.Setting the Halted bit inhibits the host controller from attempting to advance the queue between the timethe I-bit is cleared and the Active bit is set.24.9.12.3 Split Transaction IsochronousFull-speed isochronous transfers are managed using the split-transaction protocol through a USB 2.0transaction translator in a USB 2.0 hub. The host controller utilizes siTD data structure to support thespecial requirements of isochronous split-transactions. This data structure uses the scheduling model ofisochronous TDs (see Section 24.9.8, “Managing Isochronous Transfers Using iTDs,” for the operationalmodel of iTDs) with the contiguous data feature provided by queue heads. This simple arrangement allowsa single isochronous scheduling model and adds the additional feature that all data received from theendpoint (per split transaction) must land into a contiguous buffer.
