Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-130 Freescale SemiconductorIt is the responsibility of the DCD to maintain a state variable to differentiate between the DefaultFS/HSstate and the Address/Configured states. Change of state from Default to Address and the Configuredstates is part of the enumeration process described in the USB 2.0 Specification, Chapter 9, DeviceFramework.As a result of entering the Address state, the device address register (DEVICEADDR) must beprogrammed by the DCD.Entry into the Configured indicates that all endpoints to be used in the operation of the device have beenproperly initialized by programming the ENDPTCTRLn registers and initializing the associated queueheads.24.11.2.1 Bus ResetA bus reset is used by the host to initialize downstream devices. When a bus reset is detected, theUSB_controller will renegotiate its attachment speed, reset the device address to 0, and notify the DCD byinterrupt (assuming the USB Reset Interrupt Enable is set). After a reset is received, all endpoints (exceptendpoint 0) are disabled and any primed transactions will be cancelled by the device controller. Theconcept of priming will be clarified below, but the DCD must perform the following tasks when a reset isreceived:• Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and writing the samevalue back to the ENDPTSETUPSTAT register.• Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register and writingthe same value back to the ENDPTCOMPLETE register.• Cancel all primed status by waiting until all bits in the ENDPTPRIME are 0 and then writing0xFFFF_FFFF to ENDPTFLUSH.Read the reset bit in the PORTSCn register and make sure that it is still active. A USB reset will occur fora minimum of 3 ms and the DCD must reach this point in the reset cleanup before end of the reset occurs,otherwise a hardware reset of the device controller is recommended (rare.)• A hardware reset can be performed by writing a one to the USB_DR reset bit in the USBCMDreset. Note: a hardware reset will cause the device to detach from the bus by clearing the Run/Stopbit. Thus, the DCD must completely re-initialize the USB_DR after a hardware reset.Free all allocated dTDs because they will no longer be executed by the device controller. If this is the firsttime the DCD is processing a USB reset event, then it is likely that no dTDs have been allocated.At this time, the DCD may release control back to the OS because no further changes to the devicecontroller are permitted until a Port Change Detect is indicated.Table 24-80. Device Controller State Information BitsBit RegisterDCSuspend USBSTSUSB Reset Received USBSTSPort Change Detect USBSTSHigh-Speed Port PORTSC
