IEEE 1149.1 Test Access Port (JTAG)MCF5253 Reference Manual, Rev. 121-4 Freescale Semiconductorinstruction operations occur. TMS has an internal pullup so that if it is not driven low, its value will defaultto a logic level of 1. However, if TMS will not be used, it should be tied to Vdd. This pin also signals ahardware breakpoint to the processor when in the debug mode.21.3.4 Test Data Input/Development Serial Input (TDI/DSI)This is a dual-function pin. If TEST[2:0] = 001, then DSI is selected. If TEST[2:0] = 000, then TDI isselected. When used as TDI, this input signal provides the serial data port for loading the various JTAGshift registers composed of the boundary scan register, the bypass register, and the instruction register.Shifting in of data depends on the state of the JTAG controller state machine and the instruction currentlyin the instruction register. This data shift occurs on the rising edge of TCK. TDI also has an internal pullupso that if it is not driven low its value will default to a logic level of 1. However, if TDI will not be used,it should be tied to VDD.This pin also provides the single-bit communication for the debug module commands.21.3.5 Test Data Output/Development Serial Output (TDO/DSO)This is a dual-function pin. When TEST[2:0] = 001, then DSO is selected. When TEST[2:0] = 000, TDOis selected. When used as TDO, this output signal provides the serial data port for outputting data from theJTAG logic. Shifting out of data depends on the state of the JTAG controller state machine and theinstruction currently in the instruction register. This data shift occurs on the falling edge of TCK. WhenTDO is not outputting test data, it is tri-stated. TDO can also be placed in tri-state mode to allow bussedor parallel connections to other devices having JTAG.21.4 TAP ControllerThe state of TMS at the rising edge of TCK determines the current state of the TAP controller. There arebasically two paths that the TAP controller can follow: The first, for executing JTAG instructions; thesecond, for manipulating JTAG data based on the JTAG instructions. The various states of the TAPcontroller are shown in Figure 21-2. For more detail on each state, refer to the IEEE 1149.1A StandardJTAG document.NOTEFrom any state that the TAP controller is in, Test-Logic-Reset can be enteredif TMS is held high for at least five rising edges of TCK.
