UART ModulesMCF5253 Reference Manual, Rev. 115-6 Freescale Semiconductor.Figure 15-4. Transmitter and Receiver Functional Diagram15.3.2.1 TransmitterThe transmitter is enabled through the UART command register (UCR) located within the UART module.The UART module signals the CPU when it is ready to accept a character by setting the transmitter-readybit (TxRDY) in the UART status register (USR). Functional timing information for the transmitter isshown in Figure 15-5.The transmitter converts parallel data from the CPU to a serial bit stream on TxD. It automatically sendsa start bit followed by:• The programmed number of data bits• An optional parity bit• The programmed number of stop bitsThe least significant bit is sent first. Data is shifted from the transmitter output on the falling edge of theclock source.After the transmission of the stop bits, if a new character is not available in the transmitter holding register,the TxD output remains in the high (mark condition) state, and the transmitter-empty bit (TxEMP) in theUSR is set. Transmission resumes and the TxEMP bit is cleared when the CPU loads a new character intothe UART transmitter buffer (UTB). If the transmitter receives a disable command, it continues operatinguntil the character (if one is present) in the transmit-shift register is completely shifted out of transmitterWRR/WR/WWRUART SERIAL CHANNELUART COMMAND REGISTER (UCR)EXTERNAL INTERFACEUART MODE REGISTER 1 (UMR1)UART MODE REGISTER 2 (UMR2)UART STATUS REGISTER (USR)TRANSMIT HOLDING REGISTERTRANSMIT SHIFT REGISTERRECEIVER HOLDING REGISTER 1RECEIVER HOLDING REGISTER 2RECEIVER HOLDING REGISTER 3RECEIVER SHIFT REGISTERTRANSMITBUFFER (UTB)(2 REGISTERS)RECEIVEBUFFER (URB)(4 REGISTERS)FIFOTXDRXD
