Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 24-121Advance bit in the USBSTS register. If the Interrupt on Async Advance Enable bit in the USBINTRregister is set, the host controller issues a hardware interrupt at the next interrupt threshold. A detailedexplanation of this feature is described in Section 24.9.9.2, “Removing Queue Heads from AsynchronousSchedule.”24.9.14.2.4 Host System ErrorThe host controller is a bus master and any interaction between the host controller and the system mayexperience errors. The type of host error may be catastrophic to the host controller making it impossiblefor the host controller to continue in a coherent fashion. Behavior for these types of errors is to halt thehost controller. Host-based error must result in the following actions:• The Run/Stop bit in the USBCMD register is cleared.• The Host System Error and HCHalted bits in the USBSTS register are set:• If the Host System Error Enable bit in the USBINTR register is set, then the host controller issuesa hardware interrupt. This interrupt is not delayed to the next interrupt threshold.Table 24-73 summarizes the required actions taken on the various host errors.NOTEAfter a Host System Error, the software must reset the host controller usingHCReset in the USBCMD register before re-initializing and restarting thehost controller.24.10 Device Data StructuresThis section defines the interface data structures used to communicate control, status, and data betweenDevice Controller Driver (DCD) software and the Device Controller. The data structure definitions in thischapter support a 32-bit memory buffer address space. The interface consists of device Queue Heads andTransfer Descriptors.Table 24-73. Summary Behavior on Host System ErrorsCycle Type Master Abort Target Abort Data Phase ParityFrame list pointer fetch (read) Fatal Fatal FatalsiTD fetch (read) Fatal Fatal FatalsiTD status write-back (write) Fatal Fatal FataliTD fetch (read) Fatal Fatal FataliTD status write-back (write) Fatal Fatal FatalqTD fetch (read) Fatal Fatal FatalqHD status write-back (write) Fatal Fatal FatalData write Fatal Fatal FatalData read Fatal Fatal Fatal
