DMA ControllerMCF5253 Reference Manual, Rev. 114-16 Freescale Semiconductor14.7.2 Data Transfer14.7.2.1 Periphery Request OperationAll channels can initiate transfers to/from a periphery module by means of REQUEST[3:0]. Source whereREQUEST is coming from is programmed in register DMAROUTE. If the EEXT bit (DCR[30]) is set,when a REQUEST is asserted, the DMA initiates a transfer provided the channel is idle. If the CS (cyclesteal) bit is set, the read/write transaction on the bus is limited to a single transfer. If the CS bit is clear,multiple read/write transfers can occur on the bus as programmed. REQUEST does not need to be negateduntil the DONE bit (DSR[0]) is set.14.7.2.2 Auto AlignmentThis feature allows for block transfers to occur at the optimum size based on the address, byte count, andprogrammed size. To use this feature, AA in the DCR must be set. The source is auto-aligned when theSSIZE bits indicate a larger transfer size compared to DSIZE. Source alignment takes precedence over thedestination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. Theaddress register that is chosen for alignment increments regardless of the value of the increment bit.Configuration error checking is performed on the registers that are not chosen for alignment.If the BCR contains a value greater than 16, the address will determine the size of the transfer. Single byte,word or longword transfers will occur until the address is aligned to the programmed size boundary, atwhich time the programmed size accesses begin. When the BCR is less than 16 at the beginning of aread/write transfer, the number of bytes remaining will dictate the transfer size, longword, word or byte.For example:AA = 1, SAR = $0001, BCR = $00f0, SSIZE = 00 (longword) and DSIZE = 01 (byte),Because the SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on the destinationregisters. The sequence of accesses is as follows:1. Read byte from $0001—write byte, increment SAR2. Read word from $0002—write 2 bytes, increment SAR3. Read long word from $0004—write 4 bytes, increment SAR4. Repeat longwords until SAR = $00f05. Read byte from $00f0—write byte, increment SAR.If DSIZE is set to another size, then the data writes are optimized to write the largest size allowed basedon the address, but not exceeding the configured size.14.7.2.3 Bandwidth ControlThis feature makes provision to force the DMA off the bus to allow another master access. Bus arbiterdesign was simplified by making arbitration programmable. The decode of the DCR[BWC] field provides7 levels of block transfer sizes. If the BCR decrements to a value that is a multiple of the decode of theBWC, the DMA bus request negates until termination of the bus cycle. Should a request be pending, thearbiter may then choose to switch the bus to another master. If auto-alignment is enabled (DCR[AA] = 1),
