Audio Interface Module (AIM)MCF5253 Reference Manual, Rev. 117-32 Freescale Semiconductor1 L18 is bit 18 of left sample, ~L19 is inverse of bit 19 of left sample, R18 is bit 18 of right sample.2 If incoming/outgoing interface use 16, 18 bits, data is aligned at the MSB side. LSB ‘s D1-D0 or D3-D0 will read all-zero. Writtenvalues are disregarded.3 PDOR3, PDIR2 use only 16 MSB of both left and right.4 Inversion of MSB ‘s L19 and R19 translates the format from 2-complement to unsigned.(The continuous range e.g. -0x8000 to +7FFF is translated to 0 to +0xFFFF)17.7.4 Overrun and Underrun with PDIR and PDOR RegistersAll PDOR and PDIR registers have different FIFOs for left and right channels. As a result, there is alwaysthe possibility that the left and right FIFOs may go out of sync due to FIFO underruns and FIFO overrunsthat affect only one part (left or right) of any FIFO. To prevent this from happening, two hardwaremechanisms are available:1. If PDIR1, PDIR2, or PDIR3 FIFO overrun occurs on, as an example, the right half of the FIFO, thesample that caused the overrun is not written to the right half (due to overrun). Special hardwarewill make sure the next sample is not written to the left half of the FIFO. If the overrun occurs onthe left half of the FIFO, the next sample is not written to the right half of the FIFO.2. If IIS1 or IIS2 Tx FIFO, or EBU Tx FIFO underruns on, for example, the right half of the FIFO,no sample leaves that FIFO. (because it was already empty.) Special hardware ensures that the nextsample read from the left FIFO will not leave the FIFO. (No read strobe is generated). If theunderrun occurs on the left half of the FIFO, next read strobe to the right FIFO is blocked.17.7.5 Automatic Resynchronization of FIFOsAn automatic FIFO resynchronization feature is available on the MCF5253. It can be enabled or disabledseparately for every FIFO. If enabled, the hardware will check if the left and right FIFOs are in sync, andif not, it will set the filling pointer of the right FIFO to be equal to the filling pointer of the left FIFO.The operation is shown in Figure 17-17. Every FIFO auto-resync controller has a state machine with threestates:1. Off2. Stand-By3. OnIn the On state, the filling of the left FIFO is compared with the filling of right, and if they are not equal,right is made equal to left, and an interrupt is generated.
