Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-120 Freescale Semiconductor24.9.14.1.4 USB Interrupt (Interrupt on Completion (IOC))Transfer Descriptors (iTDs, siTDs, and queue heads (qTDs)) contain a bit that can be set to cause aninterrupt on their completion. The completion of the transfer associated with that schedule item causes theUSB Interrupt (USBINT) bit in the USBSTS register to be set. In addition, if a short packet is encounteredon an IN transaction associated with a queue head, then this event also causes USBINT to be set. If theUSB Interrupt Enable bit in the USBINTR register is set, a hardware interrupt is signaled to the system atthe next interrupt threshold. If the completion is because of errors, the USBERRINT bit in the USBSTSregister is also set.24.9.14.1.5 Short PacketReception of a data packet that is less than the endpoint's Max Packet size during Control, Bulk or Interrupttransfers signals the completion of the transfer. Whenever a short packet completion occurs during a queuehead execution, the USBINT bit in the USBSTS register is set. If the USB Interrupt Enable bit is set in theUSBINTR register, a hardware interrupt is signaled to the system at the next interrupt threshold.24.9.14.2 Host Controller Event InterruptsThese interrupt sources are independent of the interrupt threshold (with the one exception being theInterrupt on Async Advance.24.9.14.2.1 Port Change EventsPort registers contain status and status change bits. When the status change bits are set, the host controllersets the Port Change Detect bit in the USBSTS register. If the Port Change Interrupt Enable bit in theUSBINTR register is set, then the host controller issues a hardware interrupt. The port status change bitsinclude:• Connect Status Change• Port Enable/Disable Change• Over-current Change• Force Port Resume24.9.14.2.2 Frame List RolloverThis event indicates that the host controller has wrapped the frame list. The current programmed size ofthe frame list effects how often this interrupt occurs. If the frame list size is 1024, then the interrupt occursevery 1024 milliseconds, if it is 512, then it occurs every 512 milliseconds, etc. When a frame list rolloveris detected, the host controller sets the Frame List Rollover bit in the USBSTS register. If the Frame ListRollover Enable bit in the USBINTR register is set, the host controller issues a hardware interrupt. Thisinterrupt is not delayed to the next interrupt threshold.24.9.14.2.3 Interrupt on Async AdvanceThis event is used for deterministic removal of queue heads from the asynchronous schedule. Wheneverthe host controller advances the on-chip context of the asynchronous schedule, it evaluates the value of theInterrupt on Async Advance Doorbell bit in the USBCMD register. If it is set, it sets the Interrupt on Async
