Advanced Technology Attachment Controller (ATA)MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 23-33• PIO mode read/write operation to the ATA bus• DMA transfers with the ATA busThe operation of the peripheral is described in detail in the following sections.23.6.1 Resetting ATA BusThe ATA bus reset ATA_RST is asserted whenever bit 6 ata_rst_b of register ata_control is cleared to 0.At the same time, the ATA protocol engine is reset. When this bit is set to 1, the reset is released.23.6.2 Programming ATA Bus Timing and iordy_enThe timing the ATA interface will operate with on the ATA bus is programmable. The 24 timing registersat MBAR2 + 0x80 to MBAR2 + 0x817 are used for this. How these registers affect the timing parameterson the ATA bus, is detailed in Section 23.4, “External Signal Description.” It is allowed to reprogram theseregisters at any time when the ATA bus is idle, so before reprogramming make sure that:• bit dma_pending in ata_control register is cleared.• bit controller_idle in interrupt_pending register is set.These 2 conditions can be accomplished by first writing dma_pending to 0, then waiting untilcontroller_idle is set, then reprogram the timing parameters. If dma_pending was 1 before thereprogramming started, it should be set again after new timing is in effect to allow the drive to finish thecurrent DMA transfer.It only makes sense to reprogram the bus timing in the middle of an ongoing DMA transfer when this isnecessary because the operating system wants to change the bus clock period. (Dynamic voltage frequencyscaling).It is necessary to wait for controller_idle because a PIO read or write to the ATA bus terminates after thebus cycle with the CPU has been terminated. If the wait for controller_idle does not occur, the new timingvalues may affect a bus cycle that is still running, and cause error.The bit iordy_en in register ata_control influences whether the ATA interface will response to the iordysignal coming from the drive. To reprogram it, same rules as for the timing registers apply: Only allowedwhen dma_pending is cleared, while controller_idle is set.23.6.3 Access to ATA Bus in PIO ModeAccess to the ATA bus in PIO mode is possible after:• ata_rst_b bit in register ata_control is set.• Timing parameters have been programmed.To access the drive in PIO mode, simply read or write to the correct drive register. The bus cycle will betranslated to an ATA cycle, and the drive is accessed.When drive registers are accessed while the ATA bus is in reset, the read or write is discarded, not done.
