MCF5253 IntroductionMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 1-7— IEEE 1149.1A Test (JTAG) Module• Clocking— Clock-multiplied PLL, programmable frequency• 1.2 V Core, 3.3 V I/O• 225 pin BGA package (140 MHz)1.5 MCF5253 Functional Overview1.5.1 ColdFire CF2 CoreThe ColdFire processor Version 2 (CF2) core consists of two independent, decoupled pipeline structuresto maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stagepipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stageoperand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and thenexecutes the required function. Because the IFP and OEP pipelines are decoupled by an instruction bufferthat serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipelinefeaturing a traditional RISC data path with a dual-read-ported register feeding an arithmetic/logic unit(ALU).1.5.2 DMA ControllerThe MCF5253 provides four fully programmable DMA channels for quick data transfer. Single and dualaddress mode is supported with the ability to program bursting and cycle stealing. Data transfer isselectable as 8-, 16-, 32-, or 128-bits. Packing and unpacking is supported.Two internal audio channels and two UART’s can be used with the DMA channels. Any DMA channelcan be used with the ATA interface. All channels can perform memory to memory transfers. The DMAcontroller has a user-selectable, 24- or 16-bit counter and a programmable DMA exception handler.External requests are not supported.1.5.3 Enhanced Multiply and Accumulate Module (eMAC)The integrated eMAC unit provides a common set of DSP operations and enhances the integer multiplyinstructions in the ColdFire architecture. The eMAC provides functionality in three related areas:1. Faster signed and unsigned integer multiplies2. Multiply-accumulate operations supporting signed and unsigned operands3. Miscellaneous register operationsMultiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensionsfor signed and unsigned integers plus signed, fixed-point fractional input operands. The eMAC has asingle-clock issue for 32x32-bit multiplication instructions and implements a four-stage executionpipeline.
