FlexCAN ModuleMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 25-27• Eighth (last) bit of the error frame delimiter or overload frame delimiter25.6.7 Time StampThe value of TIMERn is sampled at the beginning of the identifier field on the CAN bus. For a messagebeing received, the time stamp will be stored in the TIMESTAMP entry of the receive message buffer atthe time the message is written into that buffer. For a message being transmitted, the TIMESTAMP entrywill be written into the transmit message buffer once the transmission has completed successfully.The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. Thisfeature allows network time synchronization to be performed. See the CANCTRLn[TSYN] bit.25.6.8 Bit TimingThe FlexCAN module CANCTRLn register configures the bit timing parameters required by the CANprotocol. The CLK_SRC, PRESDIV, RJW, PSEG1, PSEG2, and the PROPSEG fields allow the user toconfigure the bit timing parameters.The CANCTRLn[CLK_SRC] bit defines whether the module uses the internal bus clock or the output ofthe crystal oscillator via the CRIN pin. The crystal oscillator clock should be selected whenever a tighttolerance (up to 0.1%) is required for the CAN bus timing. The crystal oscillator clock has better jitterperformance than PLL generated clocks. The value of this bit should not be changed, unless the module isin disable mode (CANMCRn[MDIS] bit is set)Careful consideration should be given when selecting the external clocking scheme, the audio sectionsmay require specific input frequencies—for example, 11.2896MHz, that are not suited to meeting the CANtiming requirements, particularly at high speed communication, therefore it may required to use theexternal audio clock pin when using the CAN modules.The PRESDIV field controls a prescaler that generates the serial clock (S-clock), whose period defines thetime quantum used to compose the CAN waveform. A time quantum is the atomic unit of time handled bythe CAN engine.Figure 25-14. CAN Engine Clocking SchemeEqn. 25-5A bit time is subdivided into three segments1 (reference Figure 25-15 and Table 25-14):• SYNC_SEG: Has a fixed length of one time quantum. Signal edges are expected to happen withinthis section.1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the BoschCAN 2.0A/B protocol specification dated September 1991 for bit timing.Oscillator Clock (CRIN)CANCTRLn[CLK_SRC]Prescaler(1 .. 256) S clock10(SYSCLK)Internal Bus Clockf TqSYCLK or EXTALPRESDIV + 1( )-----------------------------------------------=
