General Purpose Timer ModulesMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 11-511.6.3 Timer Counters (TCN0, TCN1)TCN is a memory-mapped 16-bit up counter that users can read at any time. A read cycle to TCN yieldsthe current timer value and does not affect the counting operation.A write of any value to TCN causes it to reset to all zeros.11.6.4 Timer Event Registers (TER0, TER1)The TER is an 8-bit register that reports events the timer recognizes. When the timer recognizes an event,it sets the appropriate bit in the TER, regardless of the corresponding interrupt-enable bits (ORI and CE)in the TMR.TER appears as a memory-mapped register and can be read at any time.Writing a one to a bit will clear it (writing a zero does not affect the bit value); more than one bit can becleared at a time. The REF and CAP bits must be cleared before the timer will negate the IRQ to theinterrupt controller. Reset clears this register.Address MBAR+$14CMBAR+$18CAccess: Supervisor or User read/write15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 16-BIT TIMER COUNTER VALUE (COUNT15–COUNT0)WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 11-4. Timer Counter (TCNn)Address MBAR+$151MBAR+$191Access: Supervisor or User read/write7 6 5 4 3 2 1 0R REF CAPWReset 0 0 0 0 0 0 0 0Figure 11-5. Timer Event Register (TERn)Table 11-3. Timer Event Register (TERn) Field DescriptionsField Description7–2 Reserved for future use. These bits are currently 0 when read.1REFIf a one is read from the Output Reference Event bit, the counter has reached the TRR value. The ORI bit in theTMR enables the interrupt request caused by this event. Writing a one to this bit will clear the event condition.0CAPNot applicable
