Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-40 Freescale Semiconductor24.6.3.18 Endpoint Flush Register (ENDPTFLUSH), Non-EHCIThis register is not defined in the EHCI specification. This register is used by the USB OTG module onlyin device mode.Table 24-31. Endpoint Initialization (ENDPTPRIME) Register Field DescriptionsField Description31–20 Reserved.19–16PETBPrime endpoint transmit buffer. For each endpoint, a corresponding bit is used to request that a buffer prepared for atransmit operation in order to respond to a USB IN/INTERRUPT transaction. The software should write a one to thecorresponding bit when posting a new transfer descriptor to an endpoint. The hardware will automatically use this bitto begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. The hardware willclear this bit when the associated endpoint(s) is (are) successfully primed. PETB[3] (bit 19 of the register) correspondsto endpoint 3.Note: These bits will be momentarily set by the hardware during hardware re-priming operations when a dTD isretired, and the dQH is updated.15–4 Reserved.3–0PERBPrime endpoint receive buffer. For each endpoint, a corresponding bit is used to request a buffer prepare for a receiveoperation in order to respond to a USB OUT transaction. The software should write a one to the corresponding bitwhenever posting a new transfer descriptor to an endpoint. The hardware will automatically use this bit to beginparsing for a new transfer descriptor from the queue head and prepare a receive buffer. The hardware will clear thisbit when the associated endpoint(s) is (are) successfully primed.Note: These bits will be momentarily set by the hardware during hardware re-priming operations when a dTD isretired, and the dQH is updated.Address MBAR2 + 0x7B4 Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R FETBWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R FERBWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 24-30. Endpoint Flush (ENDPTFLUSH) RegisterTable 24-32. Endpoint Flush (ENDPTFLUSH) Register Field DescriptionsField Description31–20 Reserved.19–16FETBFlush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear anyprimed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue untilcompletion. The hardware will clear this register after the endpoint flush operation is successful.
