Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 24-3The module contains a chaining direct memory access (DMA) engine that reduces the interrupt load onthe application processor, and reduces the total system bus bandwidth that must be dedicated to servicingthe USB interface requirements.To reduce bus utilization by the USB even more, the module’s DMA does not have access to the CPU bus,but instead accesses a dedicated memory that can be read/written by the CPU.24.4 Modes of OperationThe module has three basic operating modes: Host, Peripheral (device), and OTG.The mode of operation is selectable by software. In Host mode, the module supports Low, Full and Highspeed USB. In Peripheral mode, only Full and High speed are supported.24.5 External SignalsThis section contains detailed descriptions of the USB interface signals.Table 24-1 describes the external signals functionality of the USB interface.24.5.1 On-Chip TransceiverThe On-Chip transceiver is a UTMI+ specification compliant transceiver. It supports High, Full, and Lowspeed data transmission, in both Host and Device mode. In addition, it contains all necessary circuitry forOTG specific functionality.Note that the USB Controller does not support Low speed operation in device mode as per USB 2.0specification.24.5.2 PHY ClocksThe built-in PHY has its own on-chip oscillator and PLL to generate the USB serial clocks. The oscillatorneeds an external 24 MHz crystal.Table 24-1. USB External SignalsSignal I/O DescriptionUSBVBUS AI Internal UTMI+ transceiver—VBUS sensing inputUSBID I Internal UTMI+ transceiver—ID pinUSBDN I/O Internal UTMI+ transceiver—DNUSBDP I/O Internal UTMI+ transceiver—DPUSB_CRIN I UTMI Internal transceiver oscillator inputUSB_CROUT O Internal UTMI transceiver oscillator outputUSBRES AI Internal UTMI transceiver—Bias current programming resistor
