Bus OperationMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 8-53. Data bus (D[31:16])4. Strobe (CSx, OE)The bus signals transition on the rising edge of BCLK. The strobe signals CSx, OE make their transitionson the falling edge of BCLK. Read data is latched on the rising edge of BCLK.The bus supports byte, word, and longword operand transfers and uses a 16-bit data port. With theMCF5253, the port size of all memory must be programmed to 16 bits, the internal transfer terminationmust be enabled, and the number of wait states must be set for the external slave being accessed byprogramming the Chip-Select Control Registers (CSCRs) and the DRAM Controller Control Registers(DCRs). For more information on programming these registers, refer to Section 10.3, “Chip SelectOperation,” and Section 7.3.1, “DRAM Controller Registers.”Figure 8-3 shows the byte lanes that external chip-select memory and DRAM should be connected to andthe sequential transfers that would occur for each memory if a longword was transferred to it. A 16-bitmemory should be connected to[31:16] of the MCF5253 data bus. For a longword transfer, the mostsignificant word D[31:16] will be transferred on lane D[31:16], followed by the least significant wordbeing transferred.Figure 8-2. Connections for External Memory Port Sizes8.5.1 Bus Cycle ExecutionWhen a bus cycle is initiated, the processor compares the address of that bus cycle with the base addressand mask configurations programmed for various memory-mapped peripherals. These include SRAM0,SRAM1, System Bus Controller 1 and 2, chip selects, and the DRAM. If no match is found, the cycle willProcessor ExternalData BusD[31:24] D[23:16]16-Bit Port Memory Byte 0 Byte 1Byte 2 Byte 38-Bit Port Memory Byte 0Driver withIndeterminate ValuesByte 1Byte 2Byte 3
